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Author	SHA1	Message	Date
Emil J. Tywoniak	8bcec792e2	ffmerge: initvals signorm compatibility fixup	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	3b1e79d312	timinginfo: special-case $specify2 in signorm invariant	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	de7f38087d	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	79386f652f	connect: remove input ports on conflict	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	f4d180e78f	opt_dff: sigma harder, FfDataSigMapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	aeaf095be4	ff: add FfDataSigMapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	df94483b9f	opt_dff: temporarily disable signorm due to muxtree traversal	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	e6dc9b4aba	tests: fix rtlil roundtrip test	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	f06d67a031	design: fix signorm commit connectivity to design	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	9c3704d5a4	cxxrtl: ignore $input_port	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	728fe21917	flatten: redo signormalization to work around fanout issue	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	2869f5bf9c	abstract: fix test signorm	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	b3baa75528	signorm: disable passes that use rewrite_sigspecs	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	246bd6c1f2	aiger: ignore $input_port	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	7528cb3157	check: stitch info about $connect ports together for driver analysis	2026-07-17 23:32:53 +02:00
Emil J. Tywoniak	9cc0997658	signorm: remove $input cells when leaving	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	23e37193b4	abstract: skip $input_port cells	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	1350c0da92	flatten: skip $input_port cells in template module	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	c8faf605f7	signorm: skip const when fixing fanout	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	cd9b1191f2	signorm: disable in passes that use swap_names	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	53b6dc5a36	opt_expr: fix invert_map	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	f6ed20664f	satgen: support $connect	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	b408a059ad	rtlil: add dump_sigmap for hacky signorm debugging	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	8457802dda	techmap: disable signorm more	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	80f2c38a3e	techmap: disable signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	8393a7d241	opt_hier: disable signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	9521b22907	timinginfo: disable output wire check due to signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	a7b62c6bc3	rtlil: forbid rewrite_sigspecs in signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	055705aebc	opt_merge_inc: re add initvals deletion	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	8a014a1f2d	synth_ice40: always read abc9 model to understand port direction	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	04311dd529	tests: adjust to input_port and init behavior (sketchy)	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	ae78170db8	tests: adjust to input_port and init behavior (sketchy)	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	df0da642d2	tests: adjust to input_port and init behavior (sketchy)	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	8d02d94b50	wreduce: fixup initvals after setPort	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	d50f9b7bb1	ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	3031dd79d9	tests: adjust to input_port and init behavior (sketchy)	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	3b956cea1b	rtlil: fix zero width SigSpec crash in signorm setPort unsetPort	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	328ffd79d0	bug2920: disable	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	479ab70890	rtlil_bufnorm: fix cell deletion deferral bug	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	f50f03d972	tests: adjust to input_port and init behavior (sketchy)	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	65dd0d59a5	check: don't fail on $input_port	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	d93ab0d07f	mem: fix signorm cell type morph	2026-07-17 23:32:34 +02:00
Jannis Harder	b84beb598f	WIP half broken snapshot	2026-07-17 23:32:20 +02:00
Jannis Harder	51fc03688a	WIP remove dead code	2026-07-17 23:31:11 +02:00
Miodrag Milanović	22c15a7ecd	Merge pull request #6034 from YosysHQ/mmicko/system_libs ... cmake: Use system libs when available	2026-07-13 15:50:10 +00:00
Miodrag Milanovic	3541e31457	Add option to use bundled libs	2026-07-13 16:50:06 +02:00
Miodrag Milanovic	30ba4328e7	Use system libs when available	2026-07-13 15:26:00 +02:00
nella	dddf137888	Merge pull request #6024 from YosysHQ/nella/scl-build-date ... Include build datetime in scl cache hash	2026-07-13 11:54:45 +00:00
Miodrag Milanović	0e82bbefe5	Merge pull request #6027 from YosysHQ/mmicko/skip_fix ... codecov: fix not skipping when pushing on	2026-07-10 16:12:03 +00:00
Miodrag Milanovic	0f8f70eb84	codecov: fix not skipping when pushing on	2026-07-10 17:55:11 +02:00