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opt_dff: sigma harder, FfDataSigMapped

This commit is contained in:
Emil J. Tywoniak 2026-03-24 11:32:42 +01:00
parent aeaf095be4
commit f4d180e78f

View file

@ -257,7 +257,7 @@ struct OptDffWorker
if (path.count(sig_s[i]) && path.at(sig_s[i])) {
ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = mbit.first->getPort(ID::B);
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
}
@ -281,7 +281,7 @@ struct OptDffWorker
ret.insert(pat);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = mbit.first->getPort(ID::B);
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
}
@ -292,7 +292,7 @@ struct OptDffWorker
ret.insert(pat);
if (sig_a[index] == q) {
RTLIL::SigSpec s = mbit.first->getPort(ID::A);
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::A));
s[index] = RTLIL::Sx;
mbit.first->setPort(ID::A, s);
}
@ -640,7 +640,7 @@ struct OptDffWorker
}
}
bool try_merge_srst(FfData &ff, Cell *cell, bool &changed)
bool try_merge_srst(FfDataSigMapped &ff, Cell *cell, bool &changed)
{
std::map<ctrls_t, std::vector<int>> groups;
std::vector<int> remaining_indices;
@ -655,9 +655,9 @@ struct OptDffWorker
if (GetSize(mbit.first->getPort(ID::S)) != 1)
break;
SigBit s = mbit.first->getPort(ID::S);
SigBit a = mbit.first->getPort(ID::A)[mbit.second];
SigBit b = mbit.first->getPort(ID::B)[mbit.second];
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))
break;
@ -693,7 +693,7 @@ struct OptDffWorker
Const val_srst = val_srst_builder.build();
for (auto &it : groups) {
FfData new_ff = ff.slice(it.second);
FfDataSigMapped new_ff = ff.slice(it.second);
Const::Builder new_val_srst_builder(new_ff.width);
for (int i = 0; i < new_ff.width; i++)
new_val_srst_builder.push_back(val_srst[it.second[i]]);
@ -730,7 +730,7 @@ struct OptDffWorker
return false;
}
bool try_merge_ce(FfData &ff, Cell *cell, bool &changed)
bool try_merge_ce(FfDataSigMapped &ff, Cell *cell, bool &changed)
{
std::map<std::pair<patterns_t, ctrls_t>, std::vector<int>> groups;
std::vector<int> remaining_indices;
@ -743,9 +743,9 @@ struct OptDffWorker
if (GetSize(mbit.first->getPort(ID::S)) != 1)
break;
SigBit s = mbit.first->getPort(ID::S);
SigBit a = mbit.first->getPort(ID::A)[mbit.second];
SigBit b = mbit.first->getPort(ID::B)[mbit.second];
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
if (a == ff.sig_q[i]) {
enables.insert(ctrl_t(s, true));
@ -773,7 +773,7 @@ struct OptDffWorker
}
for (auto &it : groups) {
FfData new_ff = ff.slice(it.second);
FfDataSigMapped new_ff = ff.slice(it.second);
ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine);
new_ff.has_ce = true;
@ -811,8 +811,8 @@ struct OptDffWorker
while (!dff_cells.empty()) {
Cell *cell = dff_cells.back();
dff_cells.pop_back();
FfData ff(&initvals, cell);
// Break down the FF into pieces.
FfDataSigMapped ff(sigmap, &initvals, cell);
bool changed = false;
if (!ff.width) {
@ -904,7 +904,7 @@ struct OptDffWorker
qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi)));
}
State check_constbit(FfData &ff, int i)
State check_constbit(FfDataSigMapped &ff, int i)
{
State val = ff.val_init[i];
if (ff.has_arst) val = combine_const(val, ff.val_arst[i]);
@ -926,14 +926,15 @@ struct OptDffWorker
QuickConeSat qcsat(modwalker);
std::vector<RTLIL::Cell*> cells_to_remove;
std::vector<FfData> ffs_to_emit;
std::vector<FfDataSigMapped> ffs_to_emit;
bool did_something = false;
for (auto cell : module->selected_cells()) {
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);
FfDataSigMapped ff(sigmap, &initvals, cell);
pool<int> removed_sigbits;
for (int i = 0; i < ff.width; i++) {