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https://github.com/YosysHQ/yosys
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opt_dff: sigma harder, FfDataSigMapped
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parent
aeaf095be4
commit
f4d180e78f
1 changed files with 19 additions and 18 deletions
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@ -257,7 +257,7 @@ struct OptDffWorker
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if (path.count(sig_s[i]) && path.at(sig_s[i])) {
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ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
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if (sig_b[i*width + index] == q) {
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RTLIL::SigSpec s = mbit.first->getPort(ID::B);
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RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
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s[i*width + index] = RTLIL::Sx;
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mbit.first->setPort(ID::B, s);
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}
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@ -281,7 +281,7 @@ struct OptDffWorker
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ret.insert(pat);
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if (sig_b[i*width + index] == q) {
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RTLIL::SigSpec s = mbit.first->getPort(ID::B);
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RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
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s[i*width + index] = RTLIL::Sx;
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mbit.first->setPort(ID::B, s);
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}
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@ -292,7 +292,7 @@ struct OptDffWorker
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ret.insert(pat);
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if (sig_a[index] == q) {
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RTLIL::SigSpec s = mbit.first->getPort(ID::A);
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RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::A));
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s[index] = RTLIL::Sx;
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mbit.first->setPort(ID::A, s);
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}
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@ -640,7 +640,7 @@ struct OptDffWorker
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}
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}
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bool try_merge_srst(FfData &ff, Cell *cell, bool &changed)
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bool try_merge_srst(FfDataSigMapped &ff, Cell *cell, bool &changed)
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{
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std::map<ctrls_t, std::vector<int>> groups;
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std::vector<int> remaining_indices;
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@ -655,9 +655,9 @@ struct OptDffWorker
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if (GetSize(mbit.first->getPort(ID::S)) != 1)
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break;
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SigBit s = mbit.first->getPort(ID::S);
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SigBit a = mbit.first->getPort(ID::A)[mbit.second];
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SigBit b = mbit.first->getPort(ID::B)[mbit.second];
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SigBit s = sigmap(mbit.first->getPort(ID::S));
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SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
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SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
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if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))
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break;
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@ -693,7 +693,7 @@ struct OptDffWorker
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Const val_srst = val_srst_builder.build();
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for (auto &it : groups) {
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FfData new_ff = ff.slice(it.second);
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FfDataSigMapped new_ff = ff.slice(it.second);
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Const::Builder new_val_srst_builder(new_ff.width);
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for (int i = 0; i < new_ff.width; i++)
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new_val_srst_builder.push_back(val_srst[it.second[i]]);
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@ -730,7 +730,7 @@ struct OptDffWorker
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return false;
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}
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bool try_merge_ce(FfData &ff, Cell *cell, bool &changed)
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bool try_merge_ce(FfDataSigMapped &ff, Cell *cell, bool &changed)
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{
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std::map<std::pair<patterns_t, ctrls_t>, std::vector<int>> groups;
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std::vector<int> remaining_indices;
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@ -743,9 +743,9 @@ struct OptDffWorker
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if (GetSize(mbit.first->getPort(ID::S)) != 1)
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break;
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SigBit s = mbit.first->getPort(ID::S);
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SigBit a = mbit.first->getPort(ID::A)[mbit.second];
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SigBit b = mbit.first->getPort(ID::B)[mbit.second];
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SigBit s = sigmap(mbit.first->getPort(ID::S));
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SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
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SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
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if (a == ff.sig_q[i]) {
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enables.insert(ctrl_t(s, true));
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@ -773,7 +773,7 @@ struct OptDffWorker
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}
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for (auto &it : groups) {
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FfData new_ff = ff.slice(it.second);
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FfDataSigMapped new_ff = ff.slice(it.second);
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ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine);
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new_ff.has_ce = true;
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@ -811,8 +811,8 @@ struct OptDffWorker
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while (!dff_cells.empty()) {
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Cell *cell = dff_cells.back();
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dff_cells.pop_back();
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FfData ff(&initvals, cell);
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// Break down the FF into pieces.
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FfDataSigMapped ff(sigmap, &initvals, cell);
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bool changed = false;
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if (!ff.width) {
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@ -904,7 +904,7 @@ struct OptDffWorker
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qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi)));
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}
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State check_constbit(FfData &ff, int i)
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State check_constbit(FfDataSigMapped &ff, int i)
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{
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State val = ff.val_init[i];
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if (ff.has_arst) val = combine_const(val, ff.val_arst[i]);
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@ -926,14 +926,15 @@ struct OptDffWorker
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QuickConeSat qcsat(modwalker);
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std::vector<RTLIL::Cell*> cells_to_remove;
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std::vector<FfData> ffs_to_emit;
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std::vector<FfDataSigMapped> ffs_to_emit;
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bool did_something = false;
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for (auto cell : module->selected_cells()) {
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if (!cell->is_builtin_ff())
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continue;
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FfData ff(&initvals, cell);
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FfDataSigMapped ff(sigmap, &initvals, cell);
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pool<int> removed_sigbits;
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for (int i = 0; i < ff.width; i++) {
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