395 commits

Author	SHA1	Message	Date
Eddie Hung	6d68972619	More comments, cleanup	2019-10-04 22:31:04 -07:00
Eddie Hung	7de9c33931	Fix TODOs	2019-10-04 22:31:04 -07:00
Eddie Hung	983068103e	Consistency	2019-10-04 22:31:04 -07:00
Eddie Hung	cf82b38478	Add comments for xilinx_dsp	2019-10-04 22:31:04 -07:00
Eddie Hung	74ef8feeaf	Fix xilinx_dsp for unsigned extensions	2019-10-04 16:46:15 -07:00
Miodrag Milanovic	c0b14cfea7	Fixes for MSVC build	2019-10-04 16:29:46 +02:00
Eddie Hung	e9645c7fa7	Fix broken CI, check reset even for constants, trim rstmux	2019-10-02 21:26:26 -07:00
Eddie Hung	d99810ad8a	Refactor peepopt_dffmux and be sensitive to \init when trimming	2019-10-02 18:01:45 -07:00
Eddie Hung	aebbfffd71	Ooops AREG and BREG to default to -1	2019-09-27 11:57:53 -07:00
Eddie Hung	26657037b8	Update doc with max cascade chain of 20	2019-09-26 14:31:02 -07:00
Eddie Hung	5b9deef10d	Do not always zero out C (e.g. during cascade breaks)	2019-09-26 13:59:05 -07:00
Eddie Hung	95f0dd57df	Update doc	2019-09-26 13:44:41 -07:00
Eddie Hung	58f31096ab	Zero out ports	2019-09-26 13:40:38 -07:00
Eddie Hung	af59856ba1	xilinx_dsp_cascade to also cascade AREG and BREG	2019-09-26 13:29:18 -07:00
Eddie Hung	832216dab0	Try recursive pmgen for P cascade	2019-09-26 12:09:57 -07:00
Eddie Hung	bd8661e024	CREG to check for \keep	2019-09-26 10:32:01 -07:00
Eddie Hung	c0bb1d22e8	Remove newline	2019-09-26 10:31:55 -07:00
Eddie Hung	f1de93edf5	Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)	2019-09-25 22:58:03 -07:00
Eddie Hung	cd8a640989	Reject if (* init *) present	2019-09-25 18:21:08 -07:00
Eddie Hung	aeb1539818	Rework xilinx_dsp postAdd for new wreduce call	2019-09-25 17:22:30 -07:00
Eddie Hung	5f8917c984	Fix memory issue since SigSpec& could be invalidated	2019-09-25 16:45:51 -07:00
Eddie Hung	486dd7c483	unextend only used in init	2019-09-25 14:05:59 -07:00
Eddie Hung	53ea5daa42	Call 'wreduce' after mul2dsp to avoid unextend()	2019-09-25 14:04:36 -07:00
Eddie Hung	e556d48d45	Set [AB]CASCREG to legal values	2019-09-23 16:00:11 -07:00
Eddie Hung	b824a56cde	Comment to explain separating CREG packing	2019-09-23 13:58:10 -07:00
Eddie Hung	15dfbc8125	Separate out CREG packing into new pattern, to avoid conflict with PREG	2019-09-23 13:27:10 -07:00
Eddie Hung	26a6c55665	Move log_debug("\n") later	2019-09-23 13:27:00 -07:00
Eddie Hung	d0dbbc2605	Move unextend initialisation later	2019-09-23 13:26:34 -07:00
Eddie Hung	a67af3d5e5	Use new port() overload once more	2019-09-23 13:00:44 -07:00
Eddie Hung	53817b8575	Use new port/param overload in pmg	2019-09-20 14:21:22 -07:00
Eddie Hung	d122083a11	Output pattern matcher items as log_debug()	2019-09-20 12:42:28 -07:00
Eddie Hung	95644b00cb	OPMODE is port not param	2019-09-20 12:37:29 -07:00
Eddie Hung	eb597431f0	Do not run xilinx_dsp_cascadeAB for now	2019-09-20 12:18:37 -07:00
Eddie Hung	0bca366bcd	WIP for xiinx_dsp_cascadeAB	2019-09-20 12:07:14 -07:00
Eddie Hung	b0ad2592be	Run until convergence	2019-09-20 12:04:16 -07:00
Eddie Hung	1b892ca1be	Cleanup ice40_dsp.pmg	2019-09-20 12:03:45 -07:00
Eddie Hung	d88903e610	Cleanup xilinx_dsp	2019-09-20 12:03:25 -07:00
Eddie Hung	1809f463fb	More exceptions	2019-09-20 12:03:10 -07:00
Eddie Hung	70c5444b25	Update doc	2019-09-20 10:07:54 -07:00
Eddie Hung	ed187ef1cf	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	2019-09-20 10:00:09 -07:00
Eddie Hung	1844498c5f	Add an overload for port/param with default value	2019-09-20 09:59:42 -07:00
Eddie Hung	a0d3ecf8c6	Small cleanup	2019-09-20 08:41:28 -07:00
Eddie Hung	8cfcaf108e	Disable support for SB_MAC16 reset since it is async	2019-09-19 22:48:57 -07:00
Eddie Hung	a59f80834f	SB_MAC16 ffCD to not pack same as ffO	2019-09-19 22:39:47 -07:00
Eddie Hung	1b88211ec6	Clarify	2019-09-19 21:58:34 -07:00
Eddie Hung	34f9a8ceb2	Update doc for ice40_dsp	2019-09-19 21:57:11 -07:00
Eddie Hung	8a94ce7aa5	Add an index	2019-09-19 20:04:44 -07:00
Eddie Hung	c83a667555	Fix width of D	2019-09-19 18:08:46 -07:00
Eddie Hung	a8bc460805	Use ID() macro	2019-09-19 16:13:22 -07:00
Eddie Hung	37b0fc17e3	Re-enable sign extension for C input	2019-09-19 15:40:17 -07:00