Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
Allows files to be cleaned with `make clean`, without which it breaks out-of-tree builds if an in-tree build has previously run and subsequently cleaned.
For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.
``` verilog
module ADC(input CLK);
```
instead of
``` verilog
module ADC(CLK);
input CLK;
```
Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.
Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```
The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Process the WRITE_MODE in the GW5A series in a more concise manner.
You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
UG303-1.0E_Arora Ⅴ Configurable Function Unit (CFU) User Guide.pdf
specifies that the only flip-flop types supported in GW5 are DFFSE,
DFFRE, DFFPE, and DFFCE.
However, the bit streams generated by the vendor IDE also contain DFF
flip-flops, which are probably the result of optimisation, so we leave
them in the list of permitted items, but add a flag that will allow the
generation of completely correct output files, acceptable for further P&
R using vendor tools (they will not allow the use of flip-flops other
than the four specified in the netlist).
In the GW5 SemiDual Port BSRAM series, the primitive does not have
RESETA and RESETB ports—they are replaced by the RESET port, so we
separate the files for BSRAM generation, especially since in the future
we may have to take into account other, as yet unexplored, differences
in BSRAM.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.
There are no functional changes, only renaming.
Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.
We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
