633 commits

Author	SHA1	Message	Date
Clifford Wolf	7bb83ae9f2	Add SVA first_match() support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 15:06:35 +01:00
Clifford Wolf	78f2cca2d9	Add SVA within support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 14:41:27 +01:00
Clifford Wolf	5555292ce2	Add support for SVA sequence intersect ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 14:26:57 +01:00
Clifford Wolf	d86e875f0f	Add get_fsm_accept_reject for parsing SVA properties ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 11:50:38 +01:00
Clifford Wolf	588ce0e34a	Simplified SVA "until" handling ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 01:51:42 +01:00
Clifford Wolf	480e8e676a	Add proper SVA seq.triggered support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-04 19:29:26 +01:00
Clifford Wolf	8dcf3d0c76	Add Verific SVA support for "seq and seq" expressions ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-04 15:08:21 +01:00
Clifford Wolf	9ab2498c55	Refactor Verific SVA importer property parser ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-04 14:29:48 +01:00
Clifford Wolf	261cf706f4	Add VerificClocking class and refactor Verific DFF handling ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-04 13:48:53 +01:00
Clifford Wolf	707ddb77bc	Add SVA support for sequence OR ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-03 16:34:28 +01:00
Clifford Wolf	cabc3c59e0	Fix handling of SVA "until seq.triggered" properties ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-02 18:17:10 +01:00
Clifford Wolf	ab791e61b3	Update SVA cheat sheet in verificsva.cc ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-02 16:05:56 +01:00
Clifford Wolf	4e5f1f59d6	Fix in Verific SVA importer handling of until_with ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-01 19:37:36 +01:00
Clifford Wolf	9a2a8cd97b	Fixes and improvements in Verific SVA importer ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-01 11:40:43 +01:00
Clifford Wolf	3c49e3c5b3	Add $rose/$fell support to Verific bindings ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-01 10:12:15 +01:00
Clifford Wolf	5ac3ee858a	Add support for PRIM_SVA_UNTIL to new SVA importer ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-28 15:32:17 +01:00
Clifford Wolf	8a1d6ccf0c	Add DFSM generator to verific SVA importer ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-28 15:05:33 +01:00
Clifford Wolf	15902d495f	Continue refactoring of Verific SVA importer code ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-28 11:45:04 +01:00
Clifford Wolf	25e33d7ab8	Major redesign of Verific SVA importer ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-27 20:33:15 +01:00
Clifford Wolf	b6fbeb0969	Add handling of verific OPER_REDUCE_NOR ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-26 15:26:01 +01:00
Clifford Wolf	2aeb4d4e12	Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-26 15:20:27 +01:00
Clifford Wolf	9cd9f5fc78	Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-26 15:02:03 +01:00
Clifford Wolf	d1cb5150aa	Add "SVA syntax cheat sheet" comment to verificsva.cc ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-26 14:31:58 +01:00
Clifford Wolf	eb67a7532b	Add $allconst and $allseq cell types ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-23 13:14:47 +01:00
Clifford Wolf	2521ed305e	Add Verific SVA support for ranges in repetition operator	2018-02-22 12:37:30 +01:00
Clifford Wolf	6d12c83d36	Add support for SVA throughout via Verific	2018-02-21 13:09:47 +01:00
Clifford Wolf	5c6247dfa6	Add support for SVA sequence concatenation ranges via verific ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-18 16:35:06 +01:00
Clifford Wolf	9d963cd29c	Add support for SVA until statements via Verific ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-18 14:57:52 +01:00
Clifford Wolf	5fa2aa2741	Move Verific SVA importer to extra C++ source file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-18 13:52:49 +01:00
Clifford Wolf	c4bf34f6ce	Merge Verific SVA preprocessor and SVA importer	2018-02-18 13:28:08 +01:00
Clifford Wolf	68a829dbcd	Merge branch 'master' of github.com:cliffordwolf/yosys	2018-02-16 14:22:11 +01:00
Clifford Wolf	2c95dfcb5b	Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction) ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-15 17:36:08 +01:00
Clifford Wolf	bc8ab3ab44	Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF	2018-02-15 15:26:37 +01:00
Clifford Wolf	6c00e064e2	Fix single-bit $stable handling in verific front-end ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-01 12:51:49 +01:00
Clifford Wolf	9af40faa0b	Add Verific attribute handling for assert/assume/cover/live/fair cells ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-31 19:06:51 +01:00
Clifford Wolf	675f53abbb	Fix permissions on verific vdb files	2018-01-28 18:52:01 +01:00
Clifford Wolf	1d8161b432	Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-23 17:42:40 +01:00
Clifford Wolf	a96c775a73	Add support for "yosys -E" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-07 16:36:13 +01:00
Clifford Wolf	26c4323d48	Merge pull request #479 from Fatsie/latch_without_data ... Some standard cell libraries include a latch with only set/reset.	2018-01-05 23:00:28 +01:00
Clifford Wolf	c80315cea4	Bugfix in hierarchy handling of blackbox module ports ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-05 13:28:45 +01:00
Staf Verhaegen	5126c6f22b	Some standard cell libraries include a latch with only set/reset.	2018-01-03 21:36:02 +00:00
Clifford Wolf	34005348b6	Bugfix in verilog_defaults argument parser	2017-12-24 17:21:37 +01:00
Clifford Wolf	ba90e08398	Add support for Verific PRIM_SVA_NOT properties	2017-12-10 01:10:03 +01:00
Clifford Wolf	e4a4c0e10c	Add Verific OPER_SVA_STABLE support	2017-12-10 00:59:44 +01:00
Clifford Wolf	27916105a9	Refactoring Verific SVA rewriter	2017-12-10 00:26:26 +01:00
Clifford Wolf	8364f509e3	Fix error handling for nested always/initial	2017-12-02 18:52:05 +01:00
Clifford Wolf	777f2881d8	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00
Clifford Wolf	5b6e52118c	Accept real-valued delay values	2017-11-18 10:01:30 +01:00
William D. Jones	abc5b4b8ce	Accommodate Windows-style paths during include-file processing.	2017-11-14 16:16:24 -05:00
Clifford Wolf	a8cf431d9c	Remove vhdl2verilog	2017-10-25 14:50:22 +02:00