3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-26 18:45:34 +00:00

Bugfix in hierarchy handling of blackbox module ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-01-05 13:28:45 +01:00
parent fefb652d56
commit c80315cea4
5 changed files with 10 additions and 9 deletions

View file

@ -1067,7 +1067,7 @@ AstModule::~AstModule()
}
// create a new parametric module (when needed) and return the name of the generated module
RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters)
RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool)
{
std::string stripped_name = name.str();

View file

@ -283,7 +283,7 @@ namespace AST
AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
virtual ~AstModule();
virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail);
virtual RTLIL::Module *clone() const;
};