mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-05 09:04:08 +00:00
Fixes and improvements in Verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
3c49e3c5b3
commit
9a2a8cd97b
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@ -60,7 +60,7 @@ using namespace Verific;
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#ifdef YOSYS_ENABLE_VERIFIC
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YOSYS_NAMESPACE_BEGIN
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bool verific_verbose;
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int verific_verbose;
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string verific_error_msg;
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void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
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@ -1422,8 +1422,8 @@ struct VerificPass : public Pass {
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log(" -extnets\n");
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log(" Resolve references to external nets by adding module ports as needed.\n");
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log("\n");
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log(" -v\n");
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log(" Verbose log messages.\n");
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log(" -v, -vv\n");
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log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
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log("\n");
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log("The following additional import options are useful for debugging the Verific\n");
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log("bindings (for Yosys and/or Verific developers):\n");
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@ -1459,7 +1459,7 @@ struct VerificPass : public Pass {
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veri_file::DefineCmdLineMacro("VERIFIC");
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veri_file::DefineCmdLineMacro("SYNTHESIS");
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verific_verbose = false;
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verific_verbose = 0;
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const char *release_str = Message::ReleaseString();
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time_t release_time = Message::ReleaseDate();
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@ -1607,7 +1607,11 @@ struct VerificPass : public Pass {
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continue;
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}
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if (args[argidx] == "-v") {
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verific_verbose = true;
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verific_verbose = 1;
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continue;
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}
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if (args[argidx] == "-vv") {
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verific_verbose = 2;
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continue;
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}
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if (args[argidx] == "-d" && argidx+1 < GetSize(args)) {
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@ -23,7 +23,7 @@
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YOSYS_NAMESPACE_BEGIN
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extern bool verific_verbose;
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extern int verific_verbose;
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extern pool<int> verific_sva_prims;
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@ -113,7 +113,6 @@ struct SvaFsm
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bool clockpol;
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SigBit trigger_sig = State::S1, disable_sig;
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SigBit accept_sig = State::Sz, reject_sig = State::Sz;
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SigBit throughout_sig = State::S1;
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bool materialized = false;
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@ -123,6 +122,9 @@ struct SvaFsm
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int startNode, acceptNode;
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vector<SvaNFsmNode> nodes;
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SigBit final_accept_sig = State::Sx;
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SigBit final_reject_sig = State::Sx;
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SvaFsm(Module *mod, SigBit clk, bool clkpol, SigBit dis = State::S0, SigBit trig = State::S1)
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{
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module = mod;
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@ -323,13 +325,14 @@ struct SvaFsm
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}
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}
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return state_sig[acceptNode];
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final_accept_sig = state_sig[acceptNode];
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return final_accept_sig;
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}
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// ----------------------------------------------------
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// Generating quantifier-based NFSM circuit to acquire reject signal
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SigBit getAnyAllRejectWorker(bool allMode)
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SigBit getAnyAllRejectWorker(bool /* allMode */)
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{
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// FIXME
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log_abort();
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@ -531,103 +534,143 @@ struct SvaFsm
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if (accept_sigptr)
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{
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if (GetSize(reject_sig) == 0)
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*accept_sigptr = State::S0;
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else if (GetSize(reject_sig) == 1)
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*accept_sigptr = reject_sig;
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if (GetSize(accept_sig) == 0)
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final_accept_sig = State::S0;
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else if (GetSize(accept_sig) == 1)
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final_accept_sig = accept_sig;
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else
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*accept_sigptr = module->ReduceOr(NEW_ID, reject_sig);
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final_accept_sig = module->ReduceOr(NEW_ID, accept_sig);
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*accept_sigptr = final_accept_sig;
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}
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if (GetSize(reject_sig) == 0)
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return State::S0;
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final_reject_sig = State::S0;
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else if (GetSize(reject_sig) == 1)
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final_reject_sig = reject_sig;
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else
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final_reject_sig = module->ReduceOr(NEW_ID, reject_sig);
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if (GetSize(reject_sig) == 1)
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return reject_sig;
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return module->ReduceOr(NEW_ID, reject_sig);
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return final_reject_sig;
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}
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// ----------------------------------------------------
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// State dump for verbose log messages
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void dump_nodes()
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{
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if (nodes.empty())
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return;
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log(" non-deterministic encoding:\n");
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for (int i = 0; i < GetSize(nodes); i++)
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{
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log(" node %d:%s\n", i, i == startNode ? " [start]" : i == acceptNode ? " [accept]" : "");
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for (auto &it : nodes[i].edges) {
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if (it.second != State::S1)
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log(" egde %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" egde -> %d\n", it.first);
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}
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for (auto &it : nodes[i].links) {
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if (it.second != State::S1)
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log(" link %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" link -> %d\n", it.first);
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}
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}
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}
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void dump_unodes()
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{
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if (unodes.empty())
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return;
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log(" unlinked non-deterministic encoding:\n");
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for (int i = 0; i < GetSize(unodes); i++)
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{
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if (!unodes[i].reachable)
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continue;
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log(" unode %d:%s\n", i, i == startNode ? " [start]" : "");
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for (auto &it : unodes[i].edges) {
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if (!it.second.empty())
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log(" egde %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" egde -> %d\n", it.first);
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}
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for (auto &ctrl : unodes[i].accept) {
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if (!ctrl.empty())
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log(" accept %s\n", log_signal(ctrl));
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else
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log(" accept\n");
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}
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}
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}
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void dump_dnodes()
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{
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if (dnodes.empty())
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return;
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log(" deterministic encoding:\n");
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for (auto &it : dnodes)
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{
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log(" dnode {");
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for (int i = 0; i < GetSize(it.first); i++)
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log("%s%d", i ? "," : "", it.first[i]);
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log("}:%s\n", GetSize(it.first) == 1 && it.first[0] == startNode ? " [start]" : "");
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log(" ctrl %s\n", log_signal(it.second.ctrl));
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for (auto &edge : it.second.edges) {
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log(" edge %s -> {", log_signal(edge.second));
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for (int i = 0; i < GetSize(edge.first); i++)
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log("%s%d", i ? "," : "", edge.first[i]);
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log("}\n");
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}
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for (auto &value : it.second.accept)
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log(" accept %s\n", log_signal(value));
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for (auto &value : it.second.reject)
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log(" reject %s\n", log_signal(value));
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}
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}
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void dump()
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{
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if (!nodes.empty())
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{
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log(" non-deterministic encoding:\n");
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for (int i = 0; i < GetSize(nodes); i++)
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{
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log(" node %d:%s\n", i, i == startNode ? " [start]" : i == acceptNode ? " [accept]" : "");
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log(" number of NFSM states: %d\n", GetSize(nodes));
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for (auto &it : nodes[i].edges) {
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if (it.second != State::S1)
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log(" egde %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" egde -> %d\n", it.first);
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}
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for (auto &it : nodes[i].links) {
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if (it.second != State::S1)
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log(" link %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" link -> %d\n", it.first);
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}
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}
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}
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if (!unodes.empty())
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{
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log(" unlinked non-deterministic encoding:\n");
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for (int i = 0; i < GetSize(unodes); i++)
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{
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if (!unodes[i].reachable)
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continue;
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log(" unode %d:%s\n", i, i == startNode ? " [start]" : "");
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for (auto &it : unodes[i].edges) {
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if (!it.second.empty())
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log(" egde %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" egde -> %d\n", it.first);
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}
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for (auto &ctrl : unodes[i].accept) {
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if (!ctrl.empty())
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log(" accept %s\n", log_signal(ctrl));
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else
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log(" accept\n");
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}
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}
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if (!unodes.empty()) {
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int count = 0;
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for (auto &unode : unodes)
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if (unode.reachable)
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count++;
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log(" number of reachable UFSM states: %d\n", count);
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}
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if (!dnodes.empty())
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{
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log(" deterministic encoding:\n");
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for (auto &it : dnodes)
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{
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log(" dnode {");
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for (int i = 0; i < GetSize(it.first); i++)
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log("%s%d", i ? "," : "", it.first[i]);
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log("}:%s\n", GetSize(it.first) == 1 && it.first[0] == startNode ? " [start]" : "");
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log(" number of DFSM states: %d\n", GetSize(dnodes));
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log(" ctrl %s\n", log_signal(it.second.ctrl));
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for (auto &edge : it.second.edges) {
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log(" edge %s -> {", log_signal(edge.second));
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for (int i = 0; i < GetSize(edge.first); i++)
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log("%s%d", i ? "," : "", edge.first[i]);
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log("}\n");
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}
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for (auto &value : it.second.accept)
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log(" accept %s\n", log_signal(value));
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for (auto &value : it.second.reject)
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log(" reject %s\n", log_signal(value));
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}
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if (verific_verbose >= 2) {
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dump_nodes();
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dump_unodes();
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dump_dnodes();
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}
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if (trigger_sig != State::S1)
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log(" trigger signal: %s\n", log_signal(trigger_sig));
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if (final_accept_sig != State::Sx)
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log(" accept signal: %s\n", log_signal(final_accept_sig));
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if (final_reject_sig != State::Sx)
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log(" reject signal: %s\n", log_signal(final_reject_sig));
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}
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};
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@ -941,12 +984,18 @@ struct VerificSvaImporter
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SigBit until_match = until_fsm.getAccept();
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SigBit not_until_match = module->Not(NEW_ID, until_match);
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Wire *extend_antecedent_match_q = module->addWire(NEW_ID);
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extend_antecedent_match_q->attributes["\\init"] = Const(0, 1);
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antecedent_match = module->Or(NEW_ID, antecedent_match, extend_antecedent_match_q);
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if (verific_verbose) {
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log(" Until FSM:\n");
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until_fsm.dump();
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}
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SigBit extend_antecedent_match = module->And(NEW_ID, not_until_match, antecedent_match);
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module->addDff(NEW_ID, clock, extend_antecedent_match, extend_antecedent_match_q, clockpol);
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Wire *antecedent_match_q = module->addWire(NEW_ID);
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antecedent_match_q->attributes["\\init"] = Const(0, 1);
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antecedent_match = module->Or(NEW_ID, antecedent_match, antecedent_match_q);
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antecedent_match = module->And(NEW_ID, antecedent_match, not_until_match);
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module->addDff(NEW_ID, clock, antecedent_match, antecedent_match_q, clockpol);
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}
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SvaFsm consequent_fsm(module, clock, clockpol, disable_iff, antecedent_match);
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