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Author SHA1 Message Date
Muthiah Annamalai (முத்து அண்ணாமலை)
7ae0b8c832
Merge branch 'YosysHQ:master' into rtlworks/script-stack/issue/3594 2023-05-20 22:49:45 -07:00
github-actions[bot]
147cceb516 Bump version 2023-05-18 00:15:34 +00:00
Muthu Annamalai
026cbcdd28 keep script-stack error logging 2023-05-17 16:49:50 +00:00
Muthiah Annamalai (முத்து அண்ணாமலை)
8d894d1100
Merge branch 'YosysHQ:master' into rtlworks/issue/3594 2023-05-17 09:24:26 -07:00
Miodrag Milanovic
c2285b3460 fix file rights 2023-05-17 13:39:57 +02:00
Miodrag Milanović
07e76fcaca
Merge pull request #3751 from RTLWorks/main/issue2525 
[YOSYS-2525] fix read_liberty newline handling #2525
 2023-05-17 13:33:34 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை)
693c609eec
Merge branch 'YosysHQ:master' into main/issue2525 2023-05-16 21:21:32 -07:00
Muthu Annamalai
665e0f6131 remove new line per maintainer request 2023-05-17 04:20:13 +00:00
Miodrag Milanović
acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498 
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
 2023-05-15 16:34:35 +02:00
Muthu Annamalai
721bd82d6f yosys> read_verilog /tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz 
Found gzip magic in file /tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz, decompressing using zlib.

1. Executing Verilog-2005 frontend: /tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz
Parsing Verilog input from `/tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz' to AST representation.
/tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz:1: ERROR: syntax error, unexpected TOK_ID
Obtained 13 stack frames.
1 | 0   yosys                               0x00000001001644ac _Z17yosys_print_tracev + 88
2 | 1   yosys                               0x0000000100164568 _Z12yosys_atexitv + 16
3 | 2   yosys                               0x0000000100205124 _ZN5YosysL22logv_error_with_prefixEPKcS1_Pc + 840
4 | 3   yosys                               0x00000001002052f4 _ZN5Yosys14log_file_errorERKNSt3__112basic_stringIcNS0_11char_traitsIcEENS0_9allocatorIcEEEEiPKcz + 96
5 | 4   yosys                               0x00000001003bc694 _ZNSt3__110__list_impINS_6vectorINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEENS5_IS7_EEEENS5_IS9_EEE5clearEv + 0
6 | 5   yosys                               0x000000010039772c _Z24frontend_verilog_yyparsev + 2164
7 | 6   yosys                               0x00000001003be520 _ZN5Yosys15VerilogFrontend7executeERPNSt3__113basic_istreamIcNS1_11char_traitsIcEEEENS1_12basic_stringIcS4_NS1_9allocatorIcEEEENS1_6vectorISB_NS9_ISB_EEEEPNS_5RTLIL6DesignE + 5556
8 | 7   yosys                               0x0000000100171c60 _ZN5Yosys8Frontend7executeENSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEEPNS_5RTLIL6DesignE + 172
9 | 8   yosys                               0x00000001001709a4 _ZN5Yosys4Pass4callEPNS_5RTLIL6DesignENSt3__16vectorINS4_12basic_stringIcNS4_11char_traitsIcEENS4_9allocatorIcEEEENS9_ISB_EEEE + 532
10 | 9   yosys                               0x0000000100170464 _ZN5Yosys4Pass4callEPNS_5RTLIL6DesignENSt3__112basic_stringIcNS4_11char_traitsIcEENS4_9allocatorIcEEEE + 1080
11 | 10  yosys                               0x000000010021479c _ZN5Yosys5shellEPNS_5RTLIL6DesignE + 320
12 | 11  yosys                               0x0000000100165374 main + 3444
13 | 12  dyld                                0x00000001016710f4 start + 520
 2023-05-13 00:49:05 -07:00
Muthu Annamalai
e5c89b641c Merge branch 'muthu/issue/3594' of ssh://143.244.178.245:/home/muthu/devel/yosys into rtlworks/issue/3594 2023-05-10 10:55:49 -07:00
Muthu Annamalai
7c4609aa7a [Backtrace] enable compile flag to trigger on at-exit; 6 frame minimum shows clean atexit when there is not much of a stack 
Obtained 6 stack frames.
1 | ./yosys(_Z17yosys_print_tracev+0x2e) [0x55c7a207830a]
2 | ./yosys(_Z12yosys_atexitv+0x9) [0x55c7a2078386]
3 | ./yosys(main+0x1c33) [0x55c7a207a020]
4 | /lib/x86_64-linux-gnu/libc.so.6(+0x23510) [0x7fae3a623510]
5 | /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0x89) [0x7fae3a6235c9]
6 | ./yosys(_start+0x25) [0x55c7a2078215]
 2023-05-10 17:54:36 +00:00
Muthu Annamalai
a52aeb0396 Merge remote-tracking branch 'origin/master' into muthu/issue/3594 2023-05-10 16:56:37 +00:00
github-actions[bot]
d82bae32be Bump version 2023-05-10 00:15:03 +00:00
Muthiah Annamalai (முத்து அண்ணாமலை)
c855502bd5
Update passes/techmap/libparse.cc 
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498

Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
 2023-05-09 06:40:21 -07:00
Miodrag Milanović
7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script 
gowin: Add all the primitives.
 2023-05-09 11:13:51 +02:00
Miodrag Milanović
5c7cc6ff06
Merge pull request #3745 from rfuest/gowin_alu 
gowin: Fix X output of $alu techmap
 2023-05-09 11:12:50 +02:00
Miodrag Milanović
226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff 
Updated the `plugin` command to better handle paths
 2023-05-09 08:46:02 +02:00
Miodrag Milanovic
f790e00478 Next dev cycle 2023-05-09 08:00:06 +02:00
Miodrag Milanovic
9c5a60eb20 Release version 0.29 2023-05-09 07:57:55 +02:00
Muthu Annamalai
8b2994a05a [YOSYS][Issue 3594] Print backtrace on abort/assert #3594 
ERROR: No such command: prox (type help for a command overview)
Error while executing script:
	Running script on file demo.ys
---------------------------------
   1 read_verilog ./tests/lut/map_not.v
   2 opt
   3 proc_clean
-->4 prox
---------------------------------
 2023-05-08 22:37:49 -07:00
Muthu Annamalai
dd5a56128a [YOSYS][Issue 3594] Print backtrace on abort/assert #3594 
ERROR: No such command: prox (type help for a command overview)
Error while executing script:
	Running script on file demo.ys
---------------------------------
   1 read_verilog ./tests/lut/map_not.v
   2 opt
   3 proc_clean
-->4 prox
---------------------------------
 2023-05-09 05:30:20 +00:00
github-actions[bot]
0469405abf Bump version 2023-05-09 00:15:34 +00:00
N. Engelhardt
266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt
0aeb6105eb
Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx 2023-05-08 16:15:13 +02:00
N. Engelhardt
ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00
Krystine Sherwin
5a4e72f57a
Fix sim writeback check for yw_cosim 
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
 2023-05-08 13:13:09 +12:00
Muthu Annamalai
17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest 2023-05-06 23:37:47 -07:00
YRabbit
8341fd450e Merge branch 'master' into all-primitives-script 2023-05-07 05:58:35 +10:00
Miodrag Milanović
4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop 
Synthesizable properties
 2023-05-05 11:03:09 +02:00
Muthu Annamalai
d2f3251528 adding unittest 2023-05-04 22:43:04 -07:00
Muthu Annamalai
81e089cb60 [YOSYS-2525] fix read_liberty newline handling #2525 
- newlines can be allowed in function parsing
 2023-05-04 22:30:27 -07:00
YRabbit
4f6a66e257 Merge branch 'master' into all-primitives-script 2023-05-05 10:21:50 +10:00
github-actions[bot]
f93671eb85 Bump version 2023-05-05 00:15:06 +00:00
Jannis Harder
32f5fca2aa
Merge pull request #3694 from daglem/struct-attributes 
Handling of attributes for struct / union variables
 2023-05-04 22:15:10 +02:00
Dag Lem
fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv 2023-05-04 14:28:21 +02:00
Dag Lem
ad437c178d Handling of attributes for struct / union variables 
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.

(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.

Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."

    always_ff @(posedge clk) begin
        if (rotate) begin
            { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };

            if (res) begin
                v0.bytes <= '0;
            end else if (w) begin
                v0.bytes[addr] <= data;
            end
        end
    end
 2023-05-03 18:44:07 +02:00
Aki Van Ness
bb240665b7
plugin: shuffled the #ifdef WITH_PYTHON's around to un-tangle the code and pulled out the check for the .py extension so it will complain if you try to load a python extension without python support 2023-05-03 03:35:55 -04:00
Aki Van Ness
572c8df9a8
plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with .so.so on the end 2023-05-03 02:22:46 -04:00
Ralf Fuest
30f1d10948 gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
YRabbit
2bab787729 Merge branch 'master' into all-primitives-script 2023-04-26 13:05:20 +10:00
Jannis Harder
7bff8b63b3 rename: Fix renaming cells in -witness mode 
This was renaming cells while iterating over them which would always
cause an assertion failure. Apparently having to rename cells to make
all witness signals public is rarely required, so this slipped through.
 2023-04-25 12:39:00 +02:00
Jannis Harder
cee3cb31b9
Merge pull request #3734 from jix/fix_unbased_unsized_const 
verilog: Fix const eval of unbased unsized constants
 2023-04-24 16:08:48 +02:00
github-actions[bot]
51dd029024 Bump version 2023-04-23 00:17:11 +00:00
Benjamin Barzen
8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2023-04-22 16:24:36 -07:00
YRabbit
a1dd794ff8 gowin: Add all the primitives. 
Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-22 17:10:53 +10:00
Jannis Harder
3cbca5064c verific: Handle non-seq properties with VerificClocking conditions 2023-04-21 17:19:42 +02:00
Jannis Harder
ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking 
This handles conditions on clocked concurrent assertions in unclocked
procedural contexts.
 2023-04-21 16:51:42 +02:00
Jannis Harder
985f4926b7 verilog: Fix const eval of unbased unsized constants 
When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.

This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.

The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
 2023-04-20 12:12:50 +02:00
github-actions[bot]
7efc50367e Bump version 2023-04-19 00:16:35 +00:00