mirror of
https://github.com/YosysHQ/yosys
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Merge branch 'master' into all-primitives-script
This commit is contained in:
commit
2bab787729
2
Makefile
2
Makefile
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@ -141,7 +141,7 @@ LDLIBS += -lrt
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endif
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endif
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YOSYS_VER := 0.28+4
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YOSYS_VER := 0.28+6
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# Note: We arrange for .gitcommit to contain the (short) commit hash in
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# tarballs generated with git-archive(1) using .gitattributes. The git repo
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@ -274,6 +274,10 @@ struct XAigerWriter
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continue;
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auto offset = i.first.offset;
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auto rhs = cell->getPort(i.first.name);
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if (offset >= rhs.size())
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continue;
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#ifndef NDEBUG
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if (ys_debug(1)) {
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static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
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@ -281,7 +285,7 @@ struct XAigerWriter
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log_id(cell->type), log_id(i.first.name), offset, d);
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}
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#endif
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arrival_times[cell->getPort(i.first.name)[offset]] = d;
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arrival_times[rhs[offset]] = d;
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}
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if (abc9_flop)
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@ -847,7 +847,7 @@ RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
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bits.resize(width);
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if (width >= 0 && width > int(bits.size())) {
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RTLIL::State extbit = RTLIL::State::S0;
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if (is_signed && !bits.empty())
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if ((is_signed || is_unsized) && !bits.empty())
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extbit = bits.back();
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while (width > int(bits.size()))
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bits.push_back(extbit);
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@ -674,8 +674,12 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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continue;
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auto offset = i.first.offset;
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auto O = module->addWire(NEW_ID);
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if (!cell->hasPort(i.first.name))
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continue;
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auto rhs = cell->getPort(i.first.name);
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if (offset >= rhs.size())
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continue;
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auto O = module->addWire(NEW_ID);
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#ifndef NDEBUG
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if (ys_debug(1)) {
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13
tests/arch/xilinx/bug3670.v
Normal file
13
tests/arch/xilinx/bug3670.v
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@ -0,0 +1,13 @@
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module bug3670(input we, output [31:0] o1, o2, output o3);
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// Completely missing port connections, where first affected port
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// (ADDRARDADDR) has a $setup delay
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RAMB36E1 ram1(.DOADO(o1));
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// Under-specified input port connections (WEA is 4 bits) which
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// has a $setup delay
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RAMB36E1 ram2(.WEA(we), .DOADO(o2));
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// Under-specified output port connections (DOADO is 32 bits)
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// with clk-to-q delay
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RAMB36E1 ram3(.DOADO(o3));
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endmodule
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3
tests/arch/xilinx/bug3670.ys
Normal file
3
tests/arch/xilinx/bug3670.ys
Normal file
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@ -0,0 +1,3 @@
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read_verilog bug3670.v
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read_verilog -lib -specify +/xilinx/cells_sim.v
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abc9
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28
tests/verilog/unbased_unsized_shift.sv
Normal file
28
tests/verilog/unbased_unsized_shift.sv
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@ -0,0 +1,28 @@
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module pass_through(
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input [63:0] inp,
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output [63:0] out
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);
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assign out = inp;
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endmodule
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module top;
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logic [63:0] s0c, s1c, sxc, s0d, s1d, sxd, d;
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pass_through pt(8, d);
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assign s0c = '0 << 8;
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assign s1c = '1 << 8;
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assign sxc = 'x << 8;
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assign s0d = '0 << d;
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assign s1d = '1 << d;
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assign sxd = 'x << d;
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always @* begin
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assert (s0c === 64'h0000_0000_0000_0000);
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assert (s1c === 64'hFFFF_FFFF_FFFF_FF00);
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assert (sxc === 64'hxxxx_xxxx_xxxx_xx00);
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assert (s0d === 64'h0000_0000_0000_0000);
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assert (s1d === 64'hFFFF_FFFF_FFFF_FF00);
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assert (sxd === 64'hxxxx_xxxx_xxxx_xx00);
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end
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endmodule
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7
tests/verilog/unbased_unsized_shift.ys
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7
tests/verilog/unbased_unsized_shift.ys
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@ -0,0 +1,7 @@
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read_verilog -sv unbased_unsized_shift.sv
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hierarchy
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proc
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flatten
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opt -full
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select -module top
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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