Merge branch 'muthu/issue/3594' of ssh://143.244.178.245:/home/muthu/devel/yosys into rtlworks/issue/3594

CHANGELOG

@@ -2,9 +2,22 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.28 .. Yosys 0.28-dev
+Yosys 0.29 .. Yosys 0.29-dev
 --------------------------
 
+Yosys 0.28 .. Yosys 0.29
+--------------------------
+ * New commands and options
+    - Added "synthprop" pass for synthesizable properties.
+
+ * Verific support
+    - Handle conditions on clocked concurrent assertions in unclocked
+      procedural contexts.
+
+ * Verilog
+    - Fix const eval of unbased unsized constants.
+    - Handling of attributes for struct / union variables.
+
 Yosys 0.27 .. Yosys 0.28
 --------------------------
  * Verilog

Makefile

@@ -24,6 +24,7 @@ DISABLE_VERIFIC_VHDL := 0
 ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
+ENABLE_BACKTRACE := 0
 
 # python wrappers
 ENABLE_PYOSYS := 0
@@ -68,6 +69,8 @@ ifeq ($(ENABLE_PYOSYS),1)
 ENABLE_LIBYOSYS := 1
 endif
 
+
+
 BINDIR := $(PREFIX)/bin
 LIBDIR := $(PREFIX)/lib/$(PROGRAM_PREFIX)yosys
 DATDIR := $(PREFIX)/share/$(PROGRAM_PREFIX)yosys
@@ -125,6 +128,11 @@ PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)
 PKG_CONFIG_PATH := $(BREW_PREFIX)/tcl-tk/lib/pkgconfig:$(PKG_CONFIG_PATH)
 export PATH := $(BREW_PREFIX)/bison/bin:$(BREW_PREFIX)/gettext/bin:$(BREW_PREFIX)/flex/bin:$(PATH)
 
+ifeq ($(ENABLE_BACKTRACE),1)
+CXXFLAGS += -DYOSYS_BACKTRACE
+endif
+
+
 # macports search paths
 else ifneq ($(shell :; command -v port),)
 PORT_PREFIX := $(patsubst %/bin/port,%,$(shell :; command -v port))
@@ -141,7 +149,7 @@ LDLIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.28+24
+YOSYS_VER := 0.29+11
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -157,7 +165,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0d6f4b0.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9c5a60e.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #

kernel/driver.cc

@@ -83,6 +83,32 @@ int getopt(int argc, char **argv, const char *optstring)
 }
 #endif
 
+#if !defined(_WIN32) || defined(__MINGW32__) || defined(YOSYS_BACKTRACE)
+#include <execinfo.h>
+void yosys_print_trace (void)
+{
+  void *array[32] = {0,};
+  char **strings;
+
+  int size = backtrace (array, 32);
+  strings = backtrace_symbols (array, size);
+  if (strings != NULL && size > 6)
+  {
+
+    fprintf (stderr,"Obtained %d stack frames.\n", size);
+    for (int i = 0; i < size; i++)
+      fprintf(stderr,"%d | %s\n", i+1, strings[i]);
+    free (strings);
+  }
+
+}
+#else
+void yosys_print_trace()
+{
+  fprintf(stderr,"Backtrace not available on this platform,\n");
+}
+#endif
+
 
 USING_YOSYS_NAMESPACE
 
@@ -174,6 +200,8 @@ extern "C" {
 
 void yosys_atexit()
 {
+  
+  yosys_print_trace();
 #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
 	if (!yosys_history_file.empty()) {
 #if defined(YOSYS_ENABLE_READLINE)

kernel/log.h

@@ -43,6 +43,7 @@
 #  endif
 #endif
 
+
 #if defined(_MSC_VER)
 // At least this is not in MSVC++ 2013.
 #  define __PRETTY_FUNCTION__ __FUNCTION__

passes/cmds/plugin.cc

@@ -41,50 +41,70 @@ std::map<std::string, std::string> loaded_plugin_aliases;
 void load_plugin(std::string filename, std::vector<std::string> aliases)
 {
 	std::string orig_filename = filename;
+	rewrite_filename(filename);
 
-	if (filename.find('/') == std::string::npos)
+	// Would something like this better be put in `rewrite_filename`?
+	if (filename.find("/") == std::string::npos)
 		filename = "./" + filename;
 
+
 	#ifdef WITH_PYTHON
-	if (!loaded_plugins.count(filename) && !loaded_python_plugins.count(filename)) {
+	const bool is_loaded = loaded_plugins.count(orig_filename) && loaded_python_plugins.count(orig_filename);
 	#else
-	if (!loaded_plugins.count(filename)) {
+	const bool is_loaded = loaded_plugins.count(orig_filename);
 	#endif
 
-		#ifdef WITH_PYTHON
-
-		boost::filesystem::path full_path(filename);
-
-		if(strcmp(full_path.extension().c_str(), ".py") == 0)
+	if (!is_loaded) {
+		// Check if we're loading a python script
+		if(filename.find(".py") != std::string::npos)
 		{
-			std::string path(full_path.parent_path().c_str());
-			filename = full_path.filename().c_str();
-			filename = filename.substr(0,filename.size()-3);
-			PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str());
-			PyErr_Print();
-			PyObject *module_p = PyImport_ImportModule(filename.c_str());
-			if(module_p == NULL)
-			{
+			#ifdef WITH_PYTHON
+				boost::filesystem::path full_path(filename);
+				std::string path(full_path.parent_path().c_str());
+				filename = full_path.filename().c_str();
+				filename = filename.substr(0,filename.size()-3);
+				PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str());
 				PyErr_Print();
-				log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str());
-				return;
-			}
-			loaded_python_plugins[orig_filename] = module_p;
-			Pass::init_register();
+				PyObject *module_p = PyImport_ImportModule(filename.c_str());
+				if(module_p == NULL)
+				{
+					PyErr_Print();
+					log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str());
+					return;
+				}
+				loaded_python_plugins[orig_filename] = module_p;
+				Pass::init_register();
+			#else
+				log_error(
+					"\n  This version of Yosys cannot load python plugins.\n"
+					"  Ensure Yosys is built with Python support to do so.\n"
+				);
+			#endif
 		} else {
-		#endif
+			// Otherwise we assume it's a native plugin
 
-		void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL);
-		if (hdl == NULL && orig_filename.find('/') == std::string::npos)
-			hdl = dlopen((proc_share_dirname() + "plugins/" + orig_filename + ".so").c_str(), RTLD_LAZY|RTLD_LOCAL);
-		if (hdl == NULL)
-			log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror());
-		loaded_plugins[orig_filename] = hdl;
-		Pass::init_register();
+			void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL);
+
+			// We were unable to open the file, try to do so from the plugin directory
+			if (hdl == NULL && orig_filename.find('/') == std::string::npos) {
+				hdl = dlopen([orig_filename]() {
+					std::string new_path = proc_share_dirname() + "plugins/" + orig_filename;
+
+					// Check if we need to append .so
+					if (new_path.find(".so") == std::string::npos)
+						new_path.append(".so");
+
+					return new_path;
+				}().c_str(), RTLD_LAZY|RTLD_LOCAL);
+			}
+
+			if (hdl == NULL)
+				log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror());
+
+			loaded_plugins[orig_filename] = hdl;
+			Pass::init_register();
 
-		#ifdef WITH_PYTHON
 		}
-		#endif
 	}
 
 	for (auto &alias : aliases)
@@ -182,4 +202,3 @@ struct PluginPass : public Pass {
 } PluginPass;
 
 YOSYS_NAMESPACE_END
-

techlibs/gowin/Makefile.inc

@@ -3,6 +3,7 @@ OBJS += techlibs/gowin/synth_gowin.o
 
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))

techlibs/gowin/arith_map.v

@@ -62,6 +62,6 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
 	  .SUM(Y[i])
 	  );
    end endgenerate
-   assign X = AA ^ BB;
+   assign X = AA ^ BB ^ {Y_WIDTH{BI}};
 endmodule
 

techlibs/gowin/cells_xtra.py

@@ -0,0 +1,76 @@
+#!/usr/bin/env python3
+
+# Base on Nexus cells_xtra.py
+
+from argparse import ArgumentParser
+import os.path
+from enum import Enum, auto
+import sys
+import re
+
+class State(Enum):
+    OUTSIDE = auto()
+    IN_MODULE = auto()
+    IN_PARAMETER = auto()
+
+_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
+          'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
+          'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
+          'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',
+          'IDES16', 'IDES4', 'IDES8', 'IOBUF', 'IVIDEO', 'LUT1', 'LUT2',
+          'LUT3', 'LUT4', 'MUX2', 'MUX2_LUT5', 'MUX2_LUT6', 'MUX2_LUT7',
+          'MUX2_LUT8', 'OBUF', 'ODDR', 'ODDRC', 'OSC', 'OSCF', 'OSCH',
+          'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4',
+          'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4',
+          'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
+          'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC'
+        }
+def xtract_cells_decl(dir, fout):
+    fname = os.path.join(dir, 'prim_sim.v')
+    with open(fname) as f:
+        state = State.OUTSIDE
+        for l in f:
+            l, _, comment = l.partition('//')
+            if l.startswith("module "):
+                cell_name = l[7:l.find('(')].strip()
+                if cell_name not in _skip:
+                    state = State.IN_MODULE
+                    fout.write(f'\nmodule {cell_name} (...);\n')
+            elif l.startswith(('input', 'output', 'inout')) and state == State.IN_MODULE:
+                fout.write(l)
+                if l[-1] != '\n':
+                    fout.write('\n')
+            elif l.startswith('parameter') and state == State.IN_MODULE:
+                fout.write(l)
+                if l.rstrip()[-1] == ',':
+                    state = State.IN_PARAMETER
+                if l[-1] != '\n':
+                    fout.write('\n')
+            elif state == State.IN_PARAMETER:
+                fout.write(l)
+                if l.rstrip()[-1] == ';':
+                    state = State.IN_MODULE
+                if l[-1] != '\n':
+                    fout.write('\n')
+            elif l.startswith('endmodule') and state == State.IN_MODULE:
+                state = State.OUTSIDE
+                fout.write('endmodule\n')
+                if l[-1] != '\n':
+                    fout.write('\n')
+
+if __name__ == '__main__':
+    parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.')
+    parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/')
+    args = parser.parse_args()
+
+    dirs = [
+        os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'),
+    ]
+
+    with open('cells_xtra.v', 'w') as fout:
+        fout.write('// Created by cells_xtra.py\n')
+        fout.write('\n')
+        for dir in dirs:
+            if not os.path.isdir(dir):
+                print(f'{dir} is not a directory')
+            xtract_cells_decl(dir, fout)

techlibs/gowin/synth_gowin.cc

@@ -207,6 +207,7 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("begin"))
 		{
 			run("read_verilog -specify -lib +/gowin/cells_sim.v");
+			run("read_verilog -specify -lib +/gowin/cells_xtra.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 

tests/arch/gowin/compare.v

@@ -0,0 +1,20 @@
+module top
+(
+    input [4:0] x,
+    input [4:0] y,
+
+    output lt,
+    output le,
+    output gt,
+    output ge,
+    output eq,
+    output ne
+);
+
+    assign lt = x < y;
+    assign le = x <= y;
+    assign gt = x > y;
+    assign ge = x >= y;
+    assign eq = x == y;
+    assign ne = x != y;
+endmodule

tests/arch/gowin/compare.ys

@@ -0,0 +1,9 @@
+read_verilog compare.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 5 t:ALU
+
+