Krystine Sherwin
7343ef159e
synth_quicklogic: Testing double_sync_ram_tdp
2023-12-04 11:17:18 +13:00
Krystine Sherwin
945e78e266
Adding double_sync_ram_tdp to blockram.v
2023-12-04 11:16:50 +13:00
Krystine Sherwin
2d6738bb10
qlf_tests: minor adjustment
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Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 09:38:48 +13:00
N. Engelhardt
1bd3678f75
remove example test
2023-12-01 14:28:50 +01:00
N. Engelhardt
c2fc33f0eb
fix test setup for synth_quicklogic memory tests
2023-12-01 14:03:07 +01:00
N. Engelhardt
190cbd54b1
fix test setup for synth_quicklogic memory tests
2023-12-01 10:47:39 +01:00
Krystine Sherwin
5634d98ccb
attempting to sim split memory tests
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and failing
2023-12-01 21:16:58 +13:00
Krystine Sherwin
d9d54e66c7
QLF_TDP36K: asymmetric simulation tests
2023-12-01 20:47:39 +13:00
Krystine Sherwin
0cd4a10c81
QLF_TDP36K: truncation tests matter
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Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
2023-12-01 17:14:01 +13:00
Krystine Sherwin
7f90fafd15
QLF_TDP36K: more basic tdp/sdp sim tests
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Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-01 17:00:15 +13:00
Krystine Sherwin
7a659bdd26
QLF_TDP36K: parameterised sim test gen
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Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-01 16:26:00 +13:00
Krystine Sherwin
b62173775c
QLF_TDP36K: test bram_tdp post synth
2023-12-01 09:52:27 +13:00
N. Engelhardt
64609afe2c
add example memory test
2023-11-30 19:35:43 +01:00
Krystine Sherwin
f810bd88f5
quicklogic: wildcard asymmetric memory tests
2023-11-30 17:33:13 +01:00
Krystine Sherwin
c54d6b29d3
tests: asymmetric sync rams now correctly asymmetric
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Also both use the same named parameters for better mirroring.
2023-11-30 17:33:13 +01:00
Krystine Sherwin
cdb20baf1f
quicklogic: testing port widths on split rams
2023-11-30 17:33:13 +01:00
Krystine Sherwin
4c03c84fa7
quicklogic: testing 1:4 assymetric memory
2023-11-30 17:33:13 +01:00
Krystine Sherwin
a1073c706e
quicklogic: fix double width read
2023-11-30 17:33:13 +01:00
Krystine Sherwin
fbf8607b97
quicklogic: Testing split TDP36K
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Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-11-30 17:33:13 +01:00
Krystine Sherwin
0cd67ce473
quicklogic: Initial blockram tests
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Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-11-30 17:33:13 +01:00
Martin Povišer
fb34167fd4
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 13:43:56 +01:00
Martin Povišer
d11a85fcba
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 11:12:55 +01:00
Martin Povišer
193144e68b
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 10:45:39 +01:00
Martin Povišer
e70122b74e
fixup! quicklogic: Add basic k6n10f tests
2023-11-29 11:20:16 +01:00
Martin Povišer
5bc587c843
quicklogic: Add k6n10f DSP test
2023-11-27 17:43:21 +01:00
Martin Povišer
502559cba4
quicklogic: Fix dffs.ys test
2023-11-27 17:27:46 +01:00
Martin Povišer
a3b3333eeb
quicklogic: Add basic k6n10f tests
2023-11-27 12:14:48 +01:00
Martin Povišer
74296e3d92
quicklogic: Move pp3 tests one level down
2023-11-27 12:05:55 +01:00
N. Engelhardt
e230a871be
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
Lofty
7ae4041e20
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 15:28:13 +00:00
N. Engelhardt
63cec22a0c
Merge pull request #3883 from phsauter/peepopt-shiftadd
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peepopt: Add `shiftadd` pattern
2023-11-07 10:42:15 +01:00
phsauter
c3b8de54da
test: add tests for shiftadd and shiftmul
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This expands the part-select tests with one additional module.
It specifically tests the different variants of the `peepopt`
optimizations `shiftadd` and `shiftmul`.
Not all these cases are actually transformed using `shiftadd`,
including them also checks if the correct variants are rejected.
2023-11-06 14:01:37 +01:00
Lofty
b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default"
2023-11-03 14:52:52 +00:00
Lofty
32082477b5
ice40, ecp5: enable ABC9 by default
2023-11-03 08:52:54 +00:00
N. Engelhardt
833b67af80
verific: import attributes on ports
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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
2023-10-20 18:31:41 +02:00
N. Engelhardt
1b6d1e9419
memory_libmap: look for ram_style attributes on surrounding signals
2023-10-19 19:23:35 +02:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 dffs test
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Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
Martin Povišer
4506e11d0f
booth: Extend test to catch bug from previous commit
2023-10-04 23:30:29 +02:00
Jannis Harder
c174597014
Fix sva_value_change_changed test for updated verific
2023-10-03 11:46:43 +02:00
Martin Povišer
b0045300fd
booth: Cut down the test
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Cut the test down from taking ~25 s to ~3 s.
2023-09-28 11:55:51 +02:00
Martin Povišer
c4762d930e
Merge pull request #3930 from povik/verific-test-memsemantics
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verific: Add test of accurate semantics in memory inference
2023-09-20 11:46:42 +02:00
Martin Povišer
99a5773911
Merge pull request #3920 from zachjs/asgn-expr
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sv: support assignments within expressions
2023-09-20 11:30:14 +02:00
Zachary Snow
28e99f2b8c
fix width of post-increment/decrement expressions
2023-09-18 23:46:06 -04:00
Zachary Snow
7d07615dee
allow attributes in front of ++/-- statements
2023-09-18 23:46:02 -04:00
Martin Povišer
8222121164
verific: Add test of accurate semantics in memory inference
2023-09-18 16:37:15 +02:00
andyfox-rushc
6d29dc659b
renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script
2023-09-08 15:34:56 -07:00
Martin Povišer
25a33d4082
techmap: Make the Booth test deterministic
2023-09-07 14:56:56 +02:00
Martin Povišer
0c2a99ca47
techmap: Test the Booth multiplier
2023-09-07 14:46:59 +02:00
Zachary Snow
4edb1a1921
sv: support assignments within expressions
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- Add support for assignments within expressions, e.g., `x[y++] = z;` or
`x = (y *= 2) - 1;`. The logic is handled entirely within the parser
by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
statements.
2023-09-05 22:27:55 -04:00
Miodrag Milanovic
a42c630264
put back previous test state, due to default change
2023-08-29 10:21:58 +02:00
