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fixup! quicklogic: Add basic k6n10f tests

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Martin Povišer 2023-11-30 10:45:39 +01:00
parent 49cee23128
commit 193144e68b
1 changed files with 1 additions and 1 deletions
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tests/arch/quicklogic/qlf_k6n10f/mux.ys
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@ -34,6 +34,6 @@ proc
equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 5 t:$lut r:WIDTH=6 %i # OOT flow does 2
select -assert-max 5 t:$lut r:WIDTH=6 %i # OOT flow does 2
select -assert-count 0 t:$lut r:WIDTH=3 %i # and here 1
select -assert-none t:$lut r:WIDTH=6 r:WIDTH=3 %u %i %% t:* %D