mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-30 07:53:16 +00:00
Code Activity

Revert "ice40, ecp5: enable ABC9 by default"

Browse source
This commit is contained in:
Lofty 2023-11-03 14:52:52 +00:00 • committed by GitHub
parent deebb82e85
commit b8b47f7c6c
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
6 changed files with 16 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

7
tests/arch/ecp5/add_sub.ys
View file

@ -4,9 +4,6 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-min 25 t:LUT4
select -assert-max 26 t:LUT4
select -assert-count 10 t:PFUMX
select -assert-count 6 t:L6MUX21
select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D
select -assert-count 10 t:LUT4
select -assert-none t:LUT4 %% t:* %D

3
tests/arch/ecp5/counter.ys
View file

@ -5,7 +5,6 @@ flatten
equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
select -assert-count 4 t:CCU2C
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:CCU2C t:TRELLIS_FF %% t:* %D
select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D

2
tests/arch/ice40/add_sub.ys
View file

@ -3,7 +3,7 @@ hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:SB_LUT4
select -assert-count 11 t:SB_LUT4
select -assert-count 6 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D

8
tests/arch/ice40/mux.ys
View file

@ -15,7 +15,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:SB_LUT4
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
@ -25,7 +25,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 6 t:SB_LUT4
select -assert-count 5 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
@ -35,7 +35,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-min 13 t:SB_LUT4
select -assert-max 14 t:SB_LUT4
select -assert-min 11 t:SB_LUT4
select -assert-max 12 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D