12 commits

Author	SHA1	Message	Date
Martin Povišer	e0fc48e196	quicklogic: Generate bram_types_sim.v at build time	2023-12-04 18:21:00 +01:00
Martin Povišer	22cc4aff51	quicklogic: Test TDP36K inference with initial data	2023-12-04 15:52:03 +01:00
N. Engelhardt	f9c8978128	add example memory test	2023-12-04 15:52:03 +01:00
Martin Povišer	e0a6a01ecb	quicklogic: Add RAM_INIT to specialized BRAM models	2023-12-04 15:52:03 +01:00
Martin Povišer	4903f99f85	quicklogic: Add missing RAM_INIT param on TDP36K sim model	2023-12-04 15:52:03 +01:00
Martin Povišer	b602c0858f	quicklogic: Set initial values on inferred TDP36K	2023-12-04 15:52:03 +01:00
Martin Povišer	532aca28ab	quicklogic: Drop blackbox off adder_carry	2023-12-04 15:52:03 +01:00
Martin Povišer	4bb4fd358e	ql_k6n10f: Remove support for parameter-configured DSP variety	2023-12-04 15:52:02 +01:00
N. Engelhardt	b80b1ab8b6	merge brams_final_map.v into brams_map.v	2023-12-04 15:52:02 +01:00
N. Engelhardt	20d864bbde	add dsp inference	2023-12-04 15:52:02 +01:00
N. Engelhardt	6682693888	change ql-bram-types pass to use mode parameter; clean up primitive libraries	2023-12-04 15:52:02 +01:00
N. Engelhardt	48c1fdc33d	add qlf_k6n10f architecture + bram inference ... (Copied from QuickLogic Yosys plugin repo)	2023-12-04 15:52:02 +01:00