859 commits

Author	SHA1	Message	Date
Eddie Hung	67f744d428	Cleanup	2019-06-05 12:28:46 -07:00
Eddie Hung	2c18d530ea	Call shregmap -tech xilinx_static	2019-06-05 12:28:26 -07:00
Eddie Hung	e473e74565	Revert "Move ff_map back after ABC for shregmap" ... This reverts commit 9b9bd4e19f.	2019-06-05 11:53:06 -07:00
Eddie Hung	94a5f4e609	Rename shregmap -tech xilinx -> xilinx_dynamic	2019-06-04 14:34:36 -07:00
Eddie Hung	82d41bc2f2	Add space between -D and _ABC	2019-06-04 11:54:08 -07:00
Eddie Hung	f0e93f33cf	Add (* abc_flop_q *) to brams_bb.v	2019-06-04 11:53:51 -07:00
Eddie Hung	6cf092641f	Fix name clash	2019-06-04 09:56:36 -07:00
Eddie Hung	e260150321	Add mux_map.v for wide mux	2019-06-04 09:51:47 -07:00
Eddie Hung	9b9bd4e19f	Move ff_map back after ABC for shregmap	2019-06-03 23:43:23 -07:00
Eddie Hung	09b778744d	Respect -nocarry	2019-06-03 23:42:30 -07:00
Eddie Hung	5afa42432f	Fix pmux2shiftx logic	2019-06-03 23:29:45 -07:00
Eddie Hung	23a73ca624	Merge mistake	2019-06-03 23:19:22 -07:00
Eddie Hung	f81a0ed92e	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-03 23:07:08 -07:00
Eddie Hung	b6e59741ae	Typo	2019-06-03 20:21:41 -07:00
Eddie Hung	02973474df	Remove extra newline	2019-06-03 20:04:47 -07:00
Eddie Hung	c9a0bac541	IS_C_INVERTED	2019-06-03 19:45:56 -07:00
Eddie Hung	0ad50332d9	Execute techmap and arith_map simultaneously	2019-06-03 19:36:09 -07:00
Eddie Hung	ebcc85b9b8	Fix `ifndef	2019-06-03 12:37:02 -07:00
Eddie Hung	0092770317	Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)	2019-06-03 12:34:55 -07:00
Eddie Hung	4da25c76b3	Ooopsie	2019-06-03 09:33:42 -07:00
Eddie Hung	9f44a71715	Consistent with xilinx	2019-06-03 09:23:43 -07:00
Eddie Hung	2228cef62f	Add flops as blackboxes	2019-05-31 18:11:46 -07:00
Eddie Hung	01f71085f2	Add FD*E_1 -> FD*E techmap rules	2019-05-31 18:11:24 -07:00
Eddie Hung	dea36d4366	Techmap flops before ABC again	2019-05-31 18:10:25 -07:00
Eddie Hung	eb08e71bd1	Merge branch 'xaig' into xc7mux	2019-05-31 13:03:03 -07:00
Eddie Hung	1ad33c3b5a	Remove whitebox attribute from DRAMs for now	2019-05-30 13:07:29 -07:00
Eddie Hung	fdfc18be91	Carry in/out to be the last input/output for chains to be preserved	2019-05-30 01:23:36 -07:00
Eddie Hung	276f5f8b81	Some more realistic delays...	2019-05-29 22:55:34 -07:00
Eddie Hung	f228621b80	Typo	2019-05-28 09:36:01 -07:00
Eddie Hung	e032e5bcde	Make MUXF{7,8} and CARRY4 whitebox	2019-05-27 23:09:06 -07:00
Eddie Hung	54e28eb3ea	Re-enable lib_whitebox	2019-05-27 23:08:55 -07:00
Eddie Hung	4311b9b583	Blackboxes	2019-05-26 11:32:02 -07:00
Eddie Hung	66701c5fcc	Muck about with LUT delays some more	2019-05-26 02:52:48 -07:00
Eddie Hung	ca5774ed40	Try new LUT delays	2019-05-24 20:39:55 -07:00
Eddie Hung	60af2ca94d	Transpose CARRY4 delays	2019-05-24 14:09:15 -07:00
Eddie Hung	52e9036d39	Merge remote-tracking branch 'origin/master' into xc7mux	2019-05-23 13:38:04 -07:00
Eddie Hung	68359bcd6f	Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux	2019-05-23 13:37:53 -07:00
Eddie Hung	99a3fee8f4	Add "min bits" and "min wports" to xilinx dram rules	2019-05-23 11:32:28 -07:00
Eddie Hung	ae89e6ab26	Add whitebox support to DRAM	2019-05-23 08:58:57 -07:00
Eddie Hung	4f44e3399b	shift register inference before mux	2019-05-22 02:36:28 -07:00
Eddie Hung	9b1078b9bd	Fix/workaround symptom unveiled by #1023	2019-05-21 18:50:02 -07:00
Eddie Hung	ee8435b820	Instead of MUXCY/XORCY use CARRY4 (with timing)	2019-05-21 16:19:45 -07:00
Eddie Hung	36a219063a	Modify LUT area cost to be same as old abc	2019-05-21 14:31:19 -07:00
Eddie Hung	fb09c6219b	Merge remote-tracking branch 'origin/master' into xc7mux	2019-05-21 14:21:00 -07:00
Clifford Wolf	c4b8575f43	Add "wreduce -keepdc", fixes #1016 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-20 15:36:13 +02:00
Sylvain Munaut	4f9183d107	ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>	2019-05-13 12:51:06 +02:00
Clifford Wolf	04ef222cfb	Add "stat -tech xilinx" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-11 09:24:52 +02:00
Ben Widawsky	05d8cc4567	Fix formatting for synth_intel.cc ... This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>	2019-05-09 08:40:05 -07:00
Clifford Wolf	09467bb9a3	Add "synth_xilinx -arch" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-07 15:04:36 +02:00
Eddie Hung	d9c4644e88	Merge remote-tracking branch 'origin/master' into clifford/specify	2019-05-03 15:05:57 -07:00