Miodrag Milanovic
ca2b3feed8
Fix ECP5 cells_sim for iverilog
2019-03-01 19:25:23 +01:00
Clifford Wolf
60e3c38054
Improve "read" error msg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:34:42 -08:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 20:27:27 -08:00
Clifford Wolf
b84febafd7
Hotfix for "make test"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:26:54 -08:00
Clifford Wolf
35e7f9979e
Merge pull request #837 from YosysHQ/clifford/fix835
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Fix multiple issues in wreduce FF handling, fixes #835
2019-02-28 17:40:38 -08:00
Clifford Wolf
e847690bda
Fix multiple issues in wreduce FF handling, fixes #835
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 17:24:46 -08:00
Elms
cd2902ab1f
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
2019-02-28 16:23:40 -08:00
Clifford Wolf
f505a41b76
Merge pull request #834 from YosysHQ/clifford/siminit
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Add "write_verilog -siminit"
2019-02-28 15:03:55 -08:00
Clifford Wolf
241901461a
Add "write_verilog -siminit"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 15:03:03 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
68a6937173
Fix pmgen for in-tree builds
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:56:05 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve
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ECP5 Improvements
2019-02-28 14:46:56 -08:00
Clifford Wolf
6d143c9a01
Merge pull request #827 from ucb-bar/firrtlfixes
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Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-28 14:45:04 -08:00
Clifford Wolf
64d91219b4
Fix pmgen for out-of-tree build
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:00:58 -08:00
Eddie Hung
1da0909662
Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960
Add SRL16 and SRL32 sim models
2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6
Fix SRL16/32 techmap off-by-one
2019-02-28 13:56:00 -08:00
Clifford Wolf
069801e441
Merge pull request #833 from YosysHQ/clifford/fix831
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Fix smt2 code generation for partially initialized memory words, fixe…
2019-02-28 13:40:27 -08:00
Clifford Wolf
f570aa5e1d
Fix smt2 code generation for partially initialized memowy words, fixes #831
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 12:15:58 -08:00
Clifford Wolf
5e94a8a127
Merge pull request #832 from YosysHQ/supercover
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Add "supercover" pass
2019-02-28 12:08:01 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
Clifford Wolf
63be3f3bab
Improvements in "supercover" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:45:13 -08:00
Clifford Wolf
a58dbcf2ba
Add "supercover" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:37:08 -08:00
Abdelrahman
3e3b115e0f
add dockerignore file
2019-02-26 21:02:02 -05:00
Abdelrahman
0a94441579
dockerize yosys
2019-02-26 20:53:31 -05:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
dfb23a79dd
Uncomment out more tests
2019-02-26 12:18:48 -08:00
Eddie Hung
7cac3b1c8b
abc9 -- multiple connections for inouts
2019-02-26 12:18:28 -08:00
Eddie Hung
8e883d92ed
write_xaiger to behave for undriven/unused inouts
2019-02-26 12:17:51 -08:00
Eddie Hung
da076344cc
parse_xaiger() to really pass single and multi-bit inout tests
2019-02-26 12:04:45 -08:00
Eddie Hung
3ea0161ae7
Add IdString::ends_with()
2019-02-26 12:04:16 -08:00
Eddie Hung
66b5f5166b
Enable two inout tests
2019-02-26 11:39:17 -08:00
Eddie Hung
8f02c846f6
parse_xaiger() to cope with multi bit inouts
2019-02-26 11:37:34 -08:00
Larry Doolittle
7a40294e93
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
Eddie Hung
967297cd57
abc9 cleanup
2019-02-25 18:40:53 -08:00
Eddie Hung
316232a7dd
parse_xaiger() to untransform $inout.out output ports
2019-02-25 18:40:23 -08:00
Eddie Hung
c492a3a1c4
write_xaiger duplicate inout port into out port with $inout.out suffix
2019-02-25 18:39:36 -08:00
Jim Lawson
171c425cf9
Fix FIRRTL to Verilog process instance subfield assignment.
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Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
2019-02-25 16:18:13 -08:00
Jim Lawson
81abb2517c
Merge remote-tracking branch 'upstream/master'
2019-02-25 16:04:20 -08:00
Eddie Hung
721f6a14fb
read_aiger to accept empty string for clk_name, passable only if no latches
2019-02-25 15:34:02 -08:00
Eddie Hung
0ca3fd6a1c
abc9 not to clean after aigmap
2019-02-25 15:31:52 -08:00
Eddie Hung
292f80d231
Cleanup abc9 code
2019-02-25 15:20:56 -08:00
Eddie Hung
65c8ccf7b5
Add broken testcases
2019-02-25 15:06:23 -08:00
Eddie Hung
51f28a6747
abc9 to call "clean" once at the end of all abc9_module() calls
2019-02-25 12:55:47 -08:00
David Shah
fa2f595cfa
ecp5: Compatibility with Migen AsyncResetSynchronizer
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-25 13:24:30 +00:00
Clifford Wolf
c258b99040
Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:41:36 +01:00
