dict is pretty slow when you don't ever need to iterate the container in
order. And the hashfunction for char* in dict hashes for every single
byte in the string, likely doing significantly more work than std::hash.
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.
We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
Used to select all modules including boxes, set when both `full` and `boxes` are true in the constructor, pulling down `full_selection`.
Add `Selection::selects_all()` method as short hand for `full_selection || complete_selection`.
Update selection operations to account for complete selections.
Add static methods to `Selection` for creating a new empty/full/complete selection to make it clearer to users when doing so.
Use said static methods to replace most instances of the `Selection` constructor.
Update `Selection::optimize` to use
New methods on Design to push/pop selection instead of accessing the selection stack directly. Includes methods for pushing a full/complete/empty selection.
Also helper methods on modules to check `is_selected` and `is_selected_whole`.
Now uses two enums, one to control whether or not to include partially selected
modules (and what to do if they are encountered), and one to control whether or
not to include boxed modules (and what to do if they are encountered).
Mark Design::selected{modules, whole_modules}() deprecated and make them
provide warnings on boxes. There are a lot of places that use them and I can't
always tell which ones support boxed modules and which don't.
The `Design::selected_*()` methods no longer unconditionally skip boxed modules. Instead, selections are now box and design aware.
The selection constructor now optionally takes a design pointer, and has a new `selects_boxes` flag. If the selection has an assigned design, then `Selection::selected_*()` will only return true for boxed modules if the selects_boxes flag is set. A warning is raised if a selection is checked and no design is set. Selections can change design via the `Selection::optimize()` method.
Most places that iterate over `Design::modules()` and check `Selection::selected_module()` should instead use `Design::selected_modules()`.
Since boxed modules should only ever be selected explicitly, and `full_selection` (now) refers to all non-boxed modules, `Selection::optimize()` will clear the `full_selection` flag if the `selects_boxes` flag is enabled, and instead explicitly selects all modules (including boxed modules). This also means that `full_selection` will only get automatically applied to a design without any boxed modules.
These changes necessitated a number of changes to `select.cc` in order to support this functionality when operating on selections, in particular when combining selections (e.g. by union or difference).
To minimize redundancy, a number of places that previously iterated over `design->modules()` now push the current selection to the design, use `design->selected_modules()`, and then pop the selection when done.
Introduce `RTLIL::NamedObject`, to allow for iterating over all members of a module with a single iterator instead of needing to iterate over wires, cells, memories, and processes separately.
Also implement `Module::selected_{memories, processes, members}()` to match wires and cells methods. The `selected_members()` method combines each of the other `selected_*()` methods into a single list.
