3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-20 07:36:39 +00:00

rtlil: Add selection helpers

New methods on Design to push/pop selection instead of accessing the selection stack directly. Includes methods for pushing a full/complete/empty selection.
Also helper methods on modules to check `is_selected` and `is_selected_whole`.
This commit is contained in:
Krystine Sherwin 2025-03-14 14:05:40 +13:00
parent 3b1b09baf6
commit a67b57bd64
No known key found for this signature in database
2 changed files with 48 additions and 0 deletions

View file

@ -1152,6 +1152,35 @@ bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
return selected_whole_module(mod->name);
}
void RTLIL::Design::push_selection(RTLIL::Selection sel)
{
sel.current_design = this;
selection_stack.push_back(sel);
}
void RTLIL::Design::push_empty_selection()
{
RTLIL::Selection sel(false, false, this);
push_selection(sel);
}
void RTLIL::Design::push_full_selection()
{
RTLIL::Selection sel(true, false, this);
push_selection(sel);
}
void RTLIL::Design::push_complete_selection()
{
RTLIL::Selection sel(true, true, this);
sel.optimize(this);
push_selection(sel);
}
void RTLIL::Design::pop_selection()
{
selection_stack.pop_back();
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
{
@ -2462,6 +2491,16 @@ bool RTLIL::Module::has_processes_warn() const
return !processes.empty();
}
bool RTLIL::Module::is_selected() const
{
return design->selected_module(this->name);
}
bool RTLIL::Module::is_selected_whole() const
{
return design->selected_whole_module(this->name);
}
std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
{
std::vector<RTLIL::Wire*> result;

View file

@ -1280,6 +1280,12 @@ struct RTLIL::Design
bool selected_module(RTLIL::Module *mod) const;
bool selected_whole_module(RTLIL::Module *mod) const;
void push_selection(RTLIL::Selection sel);
void push_empty_selection();
void push_full_selection();
void push_complete_selection();
void pop_selection();
RTLIL::Selection &selection() {
return selection_stack.back();
}
@ -1401,6 +1407,9 @@ public:
bool has_memories_warn() const;
bool has_processes_warn() const;
bool is_selected() const;
bool is_selected_whole() const;
std::vector<RTLIL::Wire*> selected_wires() const;
std::vector<RTLIL::Cell*> selected_cells() const;
std::vector<RTLIL::Memory*> selected_memories() const;