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https://github.com/YosysHQ/yosys
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Add Selection::clear() method
Use method in `select.cc` to reduce code duplication.
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@ -891,6 +891,14 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
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}
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}
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void RTLIL::Selection::clear()
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{
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full_selection = false;
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complete_selection = false;
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selected_modules.clear();
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selected_members.clear();
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}
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RTLIL::Design::Design()
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: verilog_defines (new define_map_t)
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{
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@ -1241,6 +1241,9 @@ struct RTLIL::Selection
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return !selects_all() && selected_modules.empty() && selected_members.empty();
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}
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// clear this selection, leaving it empty
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void clear();
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// create a new selection which is empty
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static Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };
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@ -159,10 +159,7 @@ static void select_all(RTLIL::Design *design, RTLIL::Selection &lhs)
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static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
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{
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if (lhs.selects_all()) {
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lhs.full_selection = false;
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lhs.complete_selection = false;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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lhs.clear();
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return;
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}
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@ -341,9 +338,8 @@ static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const
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for (auto mod : new_rhs.selected_modules)
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lhs.selected_modules.insert(mod);
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} else {
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lhs.clear();
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lhs.full_selection = true;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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}
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return;
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}
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@ -361,10 +357,7 @@ static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const
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static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
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{
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if (rhs.complete_selection) {
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lhs.full_selection = false;
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lhs.complete_selection = false;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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lhs.clear();
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return;
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}
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@ -378,9 +371,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
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lhs.selected_members.erase(mod);
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}
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} else {
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lhs.full_selection = false;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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lhs.clear();
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}
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return;
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}
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@ -435,10 +426,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
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return;
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if (rhs.empty()) {
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lhs.full_selection = false;
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lhs.complete_selection = false;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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lhs.clear();
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return;
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}
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@ -680,9 +668,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
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return;
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if (sel.full_selection) {
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sel.full_selection = false;
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sel.selected_modules.clear();
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sel.selected_members.clear();
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sel.clear();
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sel.selected_modules.insert(design->selected_active_module);
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return;
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}
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