mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 03:15:50 +00:00
Code Activity

Design::selection_stack should never be empty

Browse source 
Add a `log_assert` for it in `Design::check()`.
Remove unneeded checks in other places.
This commit is contained in:
Krystine Sherwin 2025-03-14 14:08:16 +13:00
parent 7eaf33e4da
commit add5eba9b2
No known key found for this signature in database
5 changed files with 15 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

14
kernel/rtlil.cc
View file

@ -1102,6 +1102,7 @@ void RTLIL::Design::sort()
void RTLIL::Design::check()
{
#ifndef NDEBUG
log_assert(!selection_stack.empty());
for (auto &it : modules_) {
log_assert(this == it.second->design);
log_assert(it.first == it.second->name);
@ -1125,8 +1126,6 @@ bool RTLIL::Design::selected_module(const RTLIL::IdString& mod_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
if (selection_stack.size() == 0)
return true;
return selection().selected_module(mod_name);
}
@ -1134,8 +1133,6 @@ bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
if (selection_stack.size() == 0)
return true;
return selection().selected_whole_module(mod_name);
}
@ -1143,8 +1140,6 @@ bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
if (selection_stack.size() == 0)
return true;
return selection().selected_member(mod_name, memb_name);
}
@ -1182,6 +1177,9 @@ void RTLIL::Design::push_complete_selection()
void RTLIL::Design::pop_selection()
{
selection_stack.pop_back();
// Default to a full_selection if we ran out of stack
if (selection_stack.empty())
push_full_selection();
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
@ -2366,6 +2364,10 @@ void RTLIL::Module::check()
log_assert(!packed_memids.count(memid));
packed_memids.insert(memid);
}
auto cell_mod = design->module(it.first);
if (cell_mod != nullptr) {
log_assert(!it.second->get_blackbox_attribute());
}
}
for (auto &it : processes) {

12
kernel/rtlil.h
View file

@ -1322,17 +1322,13 @@ struct RTLIL::Design
}
template<typename T1> void select(T1 *module) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection();
sel.select(module);
}
RTLIL::Selection &sel = selection();
sel.select(module);
}
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection();
sel.select(module, member);
}
RTLIL::Selection &sel = selection();
sel.select(module, member);
}

2
kernel/yosys.cc
View file

@ -679,7 +679,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
str += "yosys";
if (!design->selected_active_module.empty())
str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str());
if (!design->selection_stack.empty() && !design->full_selection()) {
if (!design->full_selection()) {
if (design->selected_active_module.empty())
str += "*";
else if (design->selection().selected_modules.size() != 1 || design->selection().selected_members.size() != 0 ||

5
passes/cmds/select.cc
View file

@ -715,8 +715,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
if (arg[0] == '%') {
if (arg == "%") {
if (design->selection_stack.size() > 0)
work_stack.push_back(design->selection());
work_stack.push_back(design->selection());
} else
if (arg == "%%") {
while (work_stack.size() > 1) {
@ -1507,7 +1506,7 @@ struct SelectPass : public Pass {
work_stack.pop_back();
}
log_assert(design->selection_stack.size() > 0);
log_assert(!design->selection_stack.empty());
if (clear_mode) {
design->pop_selection();

1
passes/techmap/aigmap.cc
View file

@ -171,7 +171,6 @@ struct AigmapPass : public Pass {
module->remove(cell);
if (select_mode) {
log_assert(!design->selection_stack.empty());
RTLIL::Selection& sel = design->selection();
sel.selected_members[module->name] = std::move(new_sel);
}