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Code Activity
17411 commits 135 branches 69 tags 58 MiB
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64 commits

Author SHA1 Message Date
Emil J. Tywoniak
0372902ad0 memory_map: don't rebuild TwineSearch 2026-06-24 13:10:10 +02:00
Emil J. Tywoniak
7c73fd62e4 twine: fix replayability, reduce TwineSearch usage 2026-06-22 17:53:19 +02:00
Emil J. Tywoniak
e71ed3007d WIP migration to twine 2026-06-19 11:39:47 +02:00
Emil J. Tywoniak
0c450ce8c8 WIP migration to twine 2026-06-18 19:27:41 +02:00
Emil J. Tywoniak
96b0ba9581 WIP migration to twine 2026-06-17 11:04:03 +02:00
Emil J. Tywoniak
c3ffbf6fae WIP 2026-06-12 00:18:53 +02:00
Emil J. Tywoniak
8e522b08c0 WIP 2026-06-11 13:17:54 +02:00
Emil J. Tywoniak
f592f2f3af WIP 2026-06-10 19:22:53 +02:00
Emil J. Tywoniak
2117af318c WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
d13dfc21f4 WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
f1edb571f2 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
Emil J. Tywoniak
3424c00cd0 twine 2026-06-10 14:53:45 +02:00
Emil J. Tywoniak
3d27e83d0f memory_map: propagate Mem src onto every generated cell 2026-06-10 14:53:42 +02:00
Robert O'Callahan
e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Robert O'Callahan
c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Martin Povišer
158fbf881e memory_map: Explain -iattr better 2024-03-06 15:15:37 +01:00
Martin Povišer
030d639201 opt_mem, memory_*: Refuse to operate in presence of processes 
Processes can contain `MemWriteAction` entries which are invisible to
most passes operating on memories but which will be lowered to write
ports later on by `proc_memwr`. For that reason we can get corrupted
RTLIL if we sequence the memory passes before `proc`. Address that by
making the affected memory passes ignore modules with processes.
 2024-02-23 12:27:53 +01:00
Jannis Harder
a2f9ebe43a memory_map: Add -formal option 
This maps memories for a global clock based formal verification flow.
This implies -keepdc, uses $ff cells for ROMs and sets hdlname
attributes.
 2022-08-16 13:37:30 +02:00
Jannis Harder
a6b440b5c9 memory_map: avoid undriven unused FF inputs for -keepdc 2022-06-28 19:05:35 +02:00
Jannis Harder
d78d807a7f memory_map: -keepdc option for formal 
Use it when invoking memory_map -rom-only from write_{smt2,btor}.
 2022-06-27 15:47:55 +02:00
Marcelina Kościelnicka
ab3a9325c3 memory_map: Add -rom-only option. 2022-06-17 16:56:11 +02:00
Marcelina Kościelnicka
01daa077a2 memory_map: Use const drivers instead of FFs for ROMs. 2022-06-17 15:17:14 +02:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
13b901bf1c memory_map: Improve start_offset handling. 
Fixes #2775.
 2021-05-31 17:45:21 +02:00
Marcelina Kościelnicka
c1a4730739 memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
afd5366fc2 extract_rdff: Add initvals parameter. 
This is not used yet, but will be needed when read port reset/initial
value support lands.
 2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka
1e8098279f memory_map: Use Mem helpers. 2020-10-21 17:51:20 +02:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
whitequark
e0def9e4d9 memory_map: add -attr option, to respect inference attributes. 
Before this commit, memory_map (which is always a part of a synth
script) would always pick up any $mem cell that was not processed
by a preceding pass and lower it down to $dff/$mux cells.
This is undesirable for two reasons:
  * If there is an explicit inference attribute set on a $mem cell,
    e.g. (* ram_block *), then it is arguably incorrect to map such
    a memory to $dff/$mux cells.
  * If memory_map tries to lower a memory that was intended to
    be mapped to a large BRAM, it often takes extraordinarily long
    time to finish, produces an extremely large log file, and outputs
    an unusable design.

After this commit, properly invoked memory_map will not map any
memory that has an explicit inference attribute specified, solving
the first issue, and alleviating the second. The default behavior
is not changed.
 2020-04-03 05:51:40 +00:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung
fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung
046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
a1c62b79d5 Avoid parameter values with size 0 ($mem cells) 2015-04-05 18:04:19 +02:00
Clifford Wolf
e9368a1d7e Various fixes for memories with offsets 2015-02-14 14:21:15 +01:00
Clifford Wolf
dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf
4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf
6ff46323a3 Improved write address decoder generation memory_map 2014-08-30 18:18:15 +02:00
Clifford Wolf
66763fad4e Using worker class in memory_map 2014-08-30 17:39:08 +02:00
Clifford Wolf
b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf
cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00