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Author	SHA1	Message	Date
Claire Xen	5e2992dae2	Merge pull request #3213 from antonblanchard/abc-typo ... abc: Fix {I} and {P} substitution	2022-03-14 16:05:23 +01:00
Miodrag Milanovic	27c5bafc95	Proper example code	2022-03-14 15:39:11 +01:00
github-actions[bot]	a502570c25	Bump version	2022-03-12 01:02:32 +00:00
Miodrag Milanović	cbece4af0c	Merge pull request #3229 from YosysHQ/micko/sim_date ... Add date parameter to enable full date/time and version info	2022-03-11 19:02:57 +01:00
Miodrag Milanović	532343dcfa	Merge pull request #3222 from zachjs/prune-linux-ci ... Prune Linux CI builds	2022-03-11 19:02:37 +01:00
Miodrag Milanović	04de9bb655	Merge pull request #3228 from YosysHQ/micko/disable_tests ... Disable tests on most of platforms	2022-03-11 19:02:19 +01:00
Claire Xenia Wolf	e21badd4b3	Add "sim -q" option ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-03-11 16:26:11 +01:00
Miodrag Milanovic	37de369ba7	Add date parameter to enable full date/time and version info	2022-03-11 16:01:59 +01:00
Claire Xenia Wolf	be32de1caa	Small fix in "sim" help message ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-03-11 15:36:23 +01:00
Miodrag Milanović	2f44683f4f	Merge pull request #3226 from YosysHQ/micko/btor2witness ... Sim support for btor2 witness files	2022-03-11 15:29:34 +01:00
Miodrag Milanovic	5204694123	FstData already do conversion to VCD	2022-03-11 15:21:36 +01:00
Miodrag Milanovic	b72c779204	Support cell name in btor witness file	2022-03-11 15:11:14 +01:00
Claire Xenia Wolf	d340f302f6	Fix handling of some formal cells in btor back-end ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-03-11 14:21:12 +01:00
Miodrag Milanovic	ebe2ee431e	handle state names of $anyconst and $anyseq	2022-03-11 14:04:02 +01:00
Zachary Snow	5e7ea57d8e	Prune Linux CI builds	2022-03-11 12:07:48 +01:00
Miodrag Milanovic	357336339a	Proper write of memory data	2022-03-11 11:19:53 +01:00
Miodrag Milanovic	75c0391f06	Disable tests on most of platforms	2022-03-10 11:05:00 +01:00
github-actions[bot]	eb8c61f033	Bump version	2022-03-10 01:11:52 +00:00
Lofty	9f7a55c99f	intel_alm: M10K write-enable is negative-true	2022-03-09 20:18:06 +00:00
Miodrag Milanovic	295b0d1899	Start work on memory init	2022-03-09 18:34:02 +01:00
Miodrag Milanovic	f37ac5d934	Fixes and error check	2022-03-09 09:48:29 +01:00
Miodrag Milanovic	ede348cdc2	cleanup	2022-03-07 16:32:32 +01:00
Miodrag Milanovic	1b1ecd4ab0	Error checks for aiger witness	2022-03-07 15:00:14 +01:00
Miodrag Milanovic	b6aca1d743	btor2 witness co-simulation	2022-03-07 13:59:36 +01:00
Miodrag Milanović	4ccc2adbda	Merge pull request #3210 from rqou/json-signed ... json: Add help message for `signed` field	2022-03-07 09:41:25 +01:00
github-actions[bot]	7ba636cb32	Bump version	2022-03-05 01:06:31 +00:00
Miodrag Milanović	a95e5d505b	Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id ... add argument for printing cell names in yosys-smtbmc	2022-03-04 16:39:12 +01:00
Miodrag Milanović	13655ddccf	Merge pull request #3206 from YosysHQ/micko/quote_remove ... Remove quotes if any from attribute	2022-03-04 16:39:01 +01:00
Miodrag Milanović	c3124023e4	Merge pull request #3207 from nakengelhardt/json_escape_quotes ... fix handling of escaped chars in json backend and frontend (mostly)	2022-03-04 13:57:32 +01:00
Miodrag Milanovic	7be7f5e02e	Next dev cycle	2022-03-04 11:37:18 +01:00
Miodrag Milanovic	07a43689d8	Release version 0.15	2022-03-04 11:36:03 +01:00
Miodrag Milanovic	66ba5ed7a5	Update ABC	2022-03-04 11:32:15 +01:00
Miodrag Milanovic	a7090e9711	Update documentation	2022-03-04 10:56:33 +01:00
Miodrag Milanović	9581b9adac	Merge pull request #3219 from YosysHQ/micko/quick_vcd ... VCD reader support by using external tool	2022-03-04 10:42:14 +01:00
Miodrag Milanović	d1fbe738a7	Merge pull request #3220 from YosysHQ/claire/simstuff ... Add writing of aiw files to "sim" command	2022-03-04 10:41:02 +01:00
github-actions[bot]	e768f7552c	Bump version	2022-03-03 01:08:21 +00:00
Miodrag Milanovic	59983eda17	Add option to ignore X only signals in output	2022-03-02 16:02:13 +01:00
Miodrag Milanovic	48b56a4f7f	Write simulation files after simulation is performed	2022-03-02 15:23:07 +01:00
Miodrag Milanovic	3818e1160d	Update CHANGELOG	2022-03-02 14:26:15 +01:00
Claire Xen	2ca69e1b88	Merge pull request #3224 from YosysHQ/micko/refactor ... Micko/refactor	2022-03-02 13:52:18 +01:00
Miodrag Milanovic	28bc88a57e	Cleanup	2022-03-02 09:39:22 +01:00
github-actions[bot]	4a38d15f0d	Bump version	2022-03-01 01:12:24 +00:00
Miodrag Milanovic	94505395a9	Refactor sim output writers	2022-02-28 18:22:39 +01:00
Miodrag Milanovic	dfd4c81eac	Quick fix	2022-02-28 11:40:06 +01:00
Claire Xenia Wolf	56b968f61c	Add writing of aiw files to "sim" command ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-28 10:50:08 +01:00
Claire Xenia Wolf	1fd3a642c9	Hotfix in AIGER witness reader state machine ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-28 10:41:44 +01:00
Miodrag Milanovic	8be09b5b24	VCD reader support by using external tool	2022-02-28 09:09:07 +01:00
Miodrag Milanović	ec4af6af2f	Merge pull request #3216 from YosysHQ/claire/simstuff ... Co-simulation improvements and fixes	2022-02-28 08:19:54 +01:00
Miodrag Milanovic	9571acc0bf	Support extended aiw format	2022-02-27 16:37:40 +01:00
Miodrag Milanovic	fca168797e	Fix for last clock edge data	2022-02-25 16:15:32 +01:00