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Proper write of memory data
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295b0d1899
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@ -326,6 +326,16 @@ struct SimInstance
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return did_something;
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}
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void set_memory_state(IdString memid, Const addr, Const data)
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{
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auto &state = mem_database[memid];
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int offset = (addr.as_int() - state.mem->start_offset) * state.mem->width;
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for (int i = 0; i < GetSize(data); i++)
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if (0 <= i+offset && i+offset < GetSize(data))
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state.data.bits[i+offset] = data.bits[i];
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}
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void update_cell(Cell *cell)
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{
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if (ff_database.count(cell))
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@ -1230,11 +1240,6 @@ struct SimWorker : SimShared
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int curr_cycle = 0;
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std::vector<std::string> parts;
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size_t len = 0;
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dict<IdString, Mem*> mem_dict;
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for (auto &mem : top->memories) {
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mem.narrow();
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mem_dict[mem.memid] = &mem;
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}
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while (!f.eof())
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{
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std::string line;
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@ -1298,15 +1303,9 @@ struct SimWorker : SimShared
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if (!c->is_mem_cell())
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log_error("Cell %s is not memory cell in module %s\n",log_id(escaped_s),log_id(topmod));
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Mem *mem = mem_dict[c->parameters.at(ID::MEMID).decode_string()];
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mem->clear_inits();
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MemInit minit;
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minit.addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
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minit.data = Const::from_string(parts[2]);
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log("[%s] = %s\n",log_signal(minit.addr), log_signal(minit.data));
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minit.en = Const(State::S1, mem->width);
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mem->inits.push_back(minit);
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mem->emit();
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Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
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Const data = Const::from_string(parts[2]);
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top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data);
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}
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break;
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}
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