mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Code Activity

Quick fix

Browse source
This commit is contained in:
Miodrag Milanovic 2022-02-28 11:40:06 +01:00
parent 56b968f61c
commit dfd4c81eac
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/sat/sim.cc
View file

@ -1304,6 +1304,8 @@ struct SimWorker : SimShared
state = 3;
break;
default:
log("Simulating cycle %d.\n", cycle);
top->setState(inputs, line);
if (cycle) {
set_inports(clock, State::S1);
set_inports(clockn, State::S0);