1052 commits

Author	SHA1	Message	Date
Clifford Wolf	5d6765a9d2	Added "insbuf" command	2016-08-02 10:37:19 +02:00
Clifford Wolf	8537c4d206	Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()	2016-07-25 16:39:25 +02:00
Clifford Wolf	b1c432af56	Improvements in CellEdgesDatabase	2016-07-24 17:21:53 +02:00
Clifford Wolf	f162b858f2	Added CellEdgesDatabase API	2016-07-24 13:59:57 +02:00
Clifford Wolf	54966679df	Moved SatHelper::setup_init() code to SatHelper::setup()	2016-07-24 12:18:39 +02:00
Clifford Wolf	34e833103b	Added $initstate support to "sat" command	2016-07-23 17:01:03 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Clifford Wolf	e92998a79c	Minor bugfix in FSM reset state detection	2016-07-12 09:46:15 +02:00
Clifford Wolf	b5a9fba0db	Further improved fsm_detect output, attempt to detect self-resetting circuits	2016-07-09 14:02:49 +02:00
Clifford Wolf	d63ffabacb	Added printing of some warning messages to fsm_detect	2016-07-09 13:23:06 +02:00
Clifford Wolf	6ed6b3cb6d	Replaced "select -assert-limit" with -assert-max and -assert-min	2016-07-01 12:24:13 +02:00
eshellko	9a742f4069	Added 'assert-limit' option for 'select' command ... For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.	2016-07-01 10:24:22 +04:00
Clifford Wolf	541083cf32	Bugfix in "abc -script" handling	2016-06-19 22:19:19 +02:00
Clifford Wolf	ca91bccb6b	Added "deminout"	2016-06-19 13:08:16 +02:00
Clifford Wolf	3380281e15	Added "dc2" to default ABC scripts	2016-06-17 20:15:35 +02:00
Clifford Wolf	f498204ae4	Added "abc -I <num> -P <num>"	2016-06-17 19:39:35 +02:00
Clifford Wolf	95757efb25	Improved support for $sop cells	2016-06-17 16:31:16 +02:00
Clifford Wolf	52bb1b968d	Added $sop cell type and "abc -sop"	2016-06-17 13:50:09 +02:00
Clifford Wolf	c3365034e9	Updated ABC to hg rev b5df6e2b76f0	2016-06-17 11:16:31 +02:00
Clifford Wolf	99edf24966	Added "nlutmap -assert"	2016-06-09 11:47:41 +02:00
Clifford Wolf	2032e6d8e4	Added "proc_mux -ifx"	2016-06-06 17:15:50 +02:00
Clifford Wolf	dcf576641b	Added "setundef -init"	2016-06-03 11:38:31 +02:00
Clifford Wolf	d2695e2bfa	Fix all undef-muxes in dlatch input cone	2016-06-02 14:37:07 +02:00
Clifford Wolf	adfc80727c	Avoid creating undef-muxes when inferring latches in proc_dlatch	2016-06-01 13:25:06 +02:00
Clifford Wolf	11f7b8a2a1	Added opt_expr support for div/mod by power-of-two	2016-05-29 12:17:36 +02:00
Clifford Wolf	611f121cb9	Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop	2016-05-27 16:33:13 +02:00
Marcus Comstedt	e22e4d59b8	Made the expansion order of hierarchy deterministic	2016-05-22 16:41:26 +02:00
Clifford Wolf	1e227caf72	Improvements and fixes in autotest.sh script and test_autotb	2016-05-20 16:58:02 +02:00
Kaj Tuomi	8c3bc2ac0d	Close opened dump file.	2016-05-19 11:53:29 +03:00
Kaj Tuomi	f6221ade95	Fix for Modelsim transcript line warp issue #164	2016-05-19 11:34:38 +03:00
Clifford Wolf	ffcdc53a18	Don't sign-extend memory bram initialization data	2016-05-15 00:05:30 +02:00
Clifford Wolf	c3f6e0ea85	Added support for "keep" attribute to shregmap	2016-05-07 09:33:16 +02:00
Clifford Wolf	aadca148da	Fixed preservation of important attributes in techmap	2016-05-06 13:59:30 +02:00
Andrew Zonenberg	3486637b19	Changed port names in greenpak shregmap	2016-05-04 17:04:50 -07:00
Clifford Wolf	9647dc3c07	Added tristate buffer support to iopadmap	2016-05-04 22:48:02 +02:00
Clifford Wolf	658f93663b	Fixed iopadmap attribute handling	2016-05-04 10:48:23 +02:00
Clifford Wolf	e01464e2ac	Added "qwp -v"	2016-04-28 23:17:30 +02:00
Clifford Wolf	0d2923cccd	Connections between inputs and inouts are driven by the input	2016-04-26 19:49:05 +02:00
Clifford Wolf	958fb29c76	Fixed test_autotb for modules with many cell ports	2016-04-25 16:37:11 +02:00
Clifford Wolf	93e107e455	Fixed proc_mux performance bug	2016-04-25 10:43:04 +02:00
Clifford Wolf	b1d6f05fa2	Fixed performance bug in proc_dlatch	2016-04-24 19:29:56 +02:00
Clifford Wolf	096c25d29d	Improvements in greenpak4 shreg mapping	2016-04-23 23:10:13 +02:00
Andrew Zonenberg	7f16784f3c	Merge https://github.com/cliffordwolf/yosys	2016-04-23 12:22:08 -07:00
Clifford Wolf	e13c66122e	Added "shregmap -zinit" for greenpak4 tech	2016-04-23 20:20:21 +02:00
Andrew Zonenberg	2849fd486e	Fixed typo in help text	2016-04-22 23:01:39 -07:00
Clifford Wolf	7311be4028	Added "shregmap -tech greenpak4"	2016-04-22 19:42:08 +02:00
Clifford Wolf	965b0d59b5	More flexible handling of initialization values	2016-04-22 12:13:06 +02:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	1565d1af69	Fixed performance bug in "share" pass	2016-04-21 19:47:25 +02:00