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https://github.com/YosysHQ/yosys
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Added $sop cell type and "abc -sop"
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parent
c3365034e9
commit
52bb1b968d
7 changed files with 171 additions and 31 deletions
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@ -32,11 +32,13 @@
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#define ABC_COMMAND_LIB "strash; scorr; ifraig; retime -o {D}; strash; dch -f; map {D}"
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#define ABC_COMMAND_CTR "strash; scorr; ifraig; retime -o {D}; strash; dch -f; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_COMMAND_LUT "strash; scorr; ifraig; retime -o; strash; dch -f; if; mfs"
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#define ABC_COMMAND_SOP "strash; scorr; ifraig; retime -o; strash; dch -f; cover"
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#define ABC_COMMAND_DFL "strash; scorr; ifraig; retime -o; strash; dch -f; map"
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#define ABC_FAST_COMMAND_LIB "retime -o {D}; map {D}"
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#define ABC_FAST_COMMAND_CTR "retime -o {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_FAST_COMMAND_LUT "retime -o; if"
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#define ABC_FAST_COMMAND_SOP "retime -o; cover"
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#define ABC_FAST_COMMAND_DFL "retime -o; map"
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#include "kernel/register.h"
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@ -593,7 +595,7 @@ struct abc_output_filter
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
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bool keepff, std::string delay_target, bool fast_mode, const std::vector<RTLIL::Cell*> &cells, bool show_tempdir)
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bool keepff, std::string delay_target, bool fast_mode, const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
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{
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module = current_module;
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map_autoidx = autoidx++;
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@ -652,6 +654,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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abc_script += "; lutpack";
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} else if (!liberty_file.empty())
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abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
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else if (sop_mode)
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abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
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else
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abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
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@ -898,9 +902,9 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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if (ifs.fail())
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log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
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bool builtin_lib = liberty_file.empty() && script_file.empty() && lut_costs.empty();
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bool builtin_lib = liberty_file.empty() && script_file.empty() && lut_costs.empty() && !sop_mode;
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RTLIL::Design *mapped_design = new RTLIL::Design;
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parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_");
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parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
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ifs.close();
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@ -1202,6 +1206,9 @@ struct AbcPass : public Pass {
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log(" for -lut/-luts (different LUT sizes):\n");
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log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
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log("\n");
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log(" for -sop:\n");
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log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
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log("\n");
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log(" otherwise:\n");
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log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
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log("\n");
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@ -1218,6 +1225,9 @@ struct AbcPass : public Pass {
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log(" for -lut/-luts:\n");
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log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
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log("\n");
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log(" for -sop:\n");
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log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
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log("\n");
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log(" otherwise:\n");
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log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
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log("\n");
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@ -1253,6 +1263,9 @@ struct AbcPass : public Pass {
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log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
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log(" 2, 3, .. inputs.\n");
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log("\n");
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log(" -sop\n");
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log(" map to sum-of-product cells\n");
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log("\n");
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// log(" -mux4, -mux8, -mux16\n");
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// log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
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// log(" (ignored when used with -liberty or -lut)\n");
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@ -1309,7 +1322,7 @@ struct AbcPass : public Pass {
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#endif
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std::string script_file, liberty_file, constr_file, clk_str, delay_target;
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bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
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bool show_tempdir = false;
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bool show_tempdir = false, sop_mode = false;
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vector<int> lut_costs;
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markgroups = false;
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@ -1393,6 +1406,10 @@ struct AbcPass : public Pass {
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}
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continue;
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}
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if (arg == "-sop") {
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sop_mode = true;
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continue;
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}
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if (arg == "-mux4") {
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map_mux4 = true;
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continue;
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@ -1466,7 +1483,7 @@ struct AbcPass : public Pass {
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if (mod->processes.size() > 0)
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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else if (!dff_mode || !clk_str.empty())
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, fast_mode, mod->selected_cells(), show_tempdir);
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
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else
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{
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assign_map.set(mod);
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@ -1611,7 +1628,7 @@ struct AbcPass : public Pass {
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en_polarity = std::get<2>(it.first);
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en_sig = assign_map(std::get<3>(it.first));
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs,
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!clk_sig.empty(), "$", keepff, delay_target, fast_mode, it.second, show_tempdir);
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!clk_sig.empty(), "$", keepff, delay_target, fast_mode, it.second, show_tempdir, sop_mode);
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assign_map.set(mod);
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}
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}
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