Added "yosys -D" feature

passes/cmds/check.cc

@@ -68,7 +68,7 @@ struct CheckPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		log_header("Executing CHECK pass (checking for obvious problems).\n");
+		log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
 
 		for (auto module : design->selected_whole_modules_warn())
 		{

passes/cmds/connwrappers.cc

@@ -198,7 +198,7 @@ struct ConnwrappersPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
+		log_header(design, "Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
 
 		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))

passes/cmds/cover.cc

@@ -124,7 +124,7 @@ struct CoverPass : public Pass {
 		extra_args(args, argidx, design);
 
 		if (do_log) {
-			log_header("Printing code coverage counters.\n");
+			log_header(design, "Printing code coverage counters.\n");
 			log("\n");
 		}
 

passes/cmds/qwp.cc

@@ -787,7 +787,7 @@ struct QwpPass : public Pass {
 		QwpConfig config;
 		xorshift32_state = 123456789;
 
-		log_header("Executing QWP pass (quadratic wirelength placer).\n");
+		log_header(design, "Executing QWP pass (quadratic wirelength placer).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/cmds/scc.cc

@@ -264,7 +264,7 @@ struct SccPass : public Pass {
 		int maxDepth = -1;
 		int expect = -1;
 
-		log_header("Executing SCC pass (detecting logic loops).\n");
+		log_header(design, "Executing SCC pass (detecting logic loops).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/cmds/show.cc

@@ -651,7 +651,7 @@ struct ShowPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Generating Graphviz representation of design.\n");
+		log_header(design, "Generating Graphviz representation of design.\n");
 		log_push();
 
 		std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
@@ -784,7 +784,7 @@ struct ShowPass : public Pass {
 		}
 
 		if (libs.size() > 0)
-			log_header("Continuing show pass.\n");
+			log_header(design, "Continuing show pass.\n");
 
 		std::string dot_file = stringf("%s.dot", prefix.c_str());
 		std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());

passes/cmds/splice.cc

@@ -341,7 +341,7 @@ struct SplicePass : public Pass {
 		if (!ports.empty() && !no_ports.empty())
 			log_cmd_error("The options -port and -no_port are exclusive!\n");
 
-		log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
+		log_header(design, "Executing SPLICE pass (creating cells for signal splicing).\n");
 
 		for (auto &mod_it : design->modules_)
 		{

passes/cmds/splitnets.cc

@@ -109,7 +109,7 @@ struct SplitnetsPass : public Pass {
 		bool flag_driver = false;
 		std::string format = "[]:";
 
-		log_header("Executing SPLITNETS pass (splitting up multi-bit signals).\n");
+		log_header(design, "Executing SPLITNETS pass (splitting up multi-bit signals).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/cmds/stat.cc

@@ -232,7 +232,7 @@ struct StatPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Printing statistics.\n");
+		log_header(design, "Printing statistics.\n");
 
 		bool width_mode = false;
 		RTLIL::Module *top_mod = NULL;

passes/cmds/torder.cc

@@ -48,7 +48,7 @@ struct TorderPass : public Pass {
 		bool noautostop = false;
 		dict<IdString, pool<IdString>> stop_db;
 
-		log_header("Executing TORDER pass (print cells in topological order).\n");
+		log_header(design, "Executing TORDER pass (print cells in topological order).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/equiv/equiv_induct.cc

@@ -198,7 +198,7 @@ struct EquivInductPass : public Pass {
 		bool model_undef = false;
 		int max_seq = 4;
 
-		log_header("Executing EQUIV_INDUCT pass.\n");
+		log_header(design, "Executing EQUIV_INDUCT pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/equiv/equiv_make.cc

@@ -464,7 +464,7 @@ struct EquivMakePass : public Pass {
 		worker.read_blacklists();
 		worker.read_encfiles();
 
-		log_header("Executing EQUIV_MAKE pass (creating equiv checking module).\n");
+		log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n");
 
 		worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2]));
 		worker.run();

passes/equiv/equiv_mark.cc

@@ -218,7 +218,7 @@ struct EquivMarkPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, Design *design)
 	{
-		log_header("Executing EQUIV_MARK pass.\n");
+		log_header(design, "Executing EQUIV_MARK pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/equiv/equiv_miter.cc

@@ -333,7 +333,7 @@ struct EquivMiterPass : public Pass {
 	found_two_modules:
 			log_cmd_error("Exactly one module must be selected for 'equiv_miter'!\n");
 
-		log_header("Executing EQUIV_MITER pass.\n");
+		log_header(design, "Executing EQUIV_MITER pass.\n");
 
 		worker.miter_module = design->addModule(worker.miter_name);
 		worker.run();

passes/equiv/equiv_purge.cc

@@ -189,7 +189,7 @@ struct EquivPurgePass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, Design *design)
 	{
-		log_header("Executing EQUIV_PURGE pass.\n");
+		log_header(design, "Executing EQUIV_PURGE pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/equiv/equiv_remove.cc

@@ -46,7 +46,7 @@ struct EquivRemovePass : public Pass {
 		bool mode_gate = false;
 		int remove_count = 0;
 
-		log_header("Executing EQUIV_REMOVE pass.\n");
+		log_header(design, "Executing EQUIV_REMOVE pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/equiv/equiv_simple.cc

@@ -277,7 +277,7 @@ struct EquivSimplePass : public Pass {
 		int success_counter = 0;
 		int max_seq = 1;
 
-		log_header("Executing EQUIV_SIMPLE pass.\n");
+		log_header(design, "Executing EQUIV_SIMPLE pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/equiv/equiv_status.cc

@@ -41,7 +41,7 @@ struct EquivStatusPass : public Pass {
 		bool assert_mode = false;
 		int unproven_count = 0;
 
-		log_header("Executing EQUIV_STATUS pass.\n");
+		log_header(design, "Executing EQUIV_STATUS pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/equiv/equiv_struct.cc

@@ -321,7 +321,7 @@ struct EquivStructPass : public Pass {
 		bool mode_fwd = false;
 		int max_iter = -1;
 
-		log_header("Executing EQUIV_STRUCT pass.\n");
+		log_header(design, "Executing EQUIV_STRUCT pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/fsm/fsm.cc

@@ -76,7 +76,7 @@ struct FsmPass : public Pass {
 		std::string encfile_opt;
 		std::string encoding_opt;
 
-		log_header("Executing FSM pass (extract and optimize FSM).\n");
+		log_header(design, "Executing FSM pass (extract and optimize FSM).\n");
 		log_push();
 
 		size_t argidx;

passes/fsm/fsm_detect.cc

@@ -154,7 +154,7 @@ struct FsmDetectPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_DETECT pass (finding FSMs in design).\n");
+		log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
 		extra_args(args, 1, design);
 
 		CellTypes ct;

passes/fsm/fsm_expand.cc

@@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
+		log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_) {

passes/fsm/fsm_export.cc

@@ -152,7 +152,7 @@ struct FsmExportPass : public Pass {
 		bool flag_origenc = false;
 		size_t argidx;
 
-		log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
+		log_header(design, "Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
 
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			arg = args[argidx];

passes/fsm/fsm_extract.cc

@@ -416,7 +416,7 @@ struct FsmExtractPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_EXTRACT pass (extracting FSM from design).\n");
+		log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
 		extra_args(args, 1, design);
 
 		CellTypes ct;

passes/fsm/fsm_info.cc

@@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
+		log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_)

passes/fsm/fsm_map.cc

@@ -335,7 +335,7 @@ struct FsmMapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
+		log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_) {

passes/fsm/fsm_opt.cc

@@ -336,7 +336,7 @@ struct FsmOptPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n");
+		log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_) {

passes/fsm/fsm_recode.cc

@@ -157,7 +157,7 @@ struct FsmRecodePass : public Pass {
 		FILE *encfile = NULL;
 		std::string default_encoding;
 
-		log_header("Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
+		log_header(design, "Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];

passes/hierarchy/hierarchy.cc

@@ -396,7 +396,7 @@ struct HierarchyPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing HIERARCHY pass (managing design hierarchy).\n");
+		log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
 
 		bool flag_check = false;
 		bool purge_lib = false;
@@ -506,7 +506,7 @@ struct HierarchyPass : public Pass {
 					top_mod = mod_it.second;
 
 		if (top_mod == nullptr && auto_top_mode) {
-			log_header("Finding top of design hierarchy..\n");
+			log_header(design, "Finding top of design hierarchy..\n");
 			dict<Module*, int> db;
 			for (Module *mod : design->selected_modules()) {
 				int score = find_top_mod_score(design, mod, db);
@@ -525,7 +525,7 @@ struct HierarchyPass : public Pass {
 
 			std::set<RTLIL::Module*> used_modules;
 			if (top_mod != NULL) {
-				log_header("Analyzing design hierarchy..\n");
+				log_header(design, "Analyzing design hierarchy..\n");
 				hierarchy_worker(design, used_modules, top_mod, 0);
 			} else {
 				for (auto mod : design->modules())
@@ -539,7 +539,7 @@ struct HierarchyPass : public Pass {
 		}
 
 		if (top_mod != NULL) {
-			log_header("Analyzing design hierarchy..\n");
+			log_header(design, "Analyzing design hierarchy..\n");
 			hierarchy_clean(design, top_mod, purge_lib);
 		}
 

passes/hierarchy/singleton.cc

@@ -43,7 +43,7 @@ struct SingletonPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing SINGLETON pass (creating singleton modules).\n");
+		log_header(design, "Executing SINGLETON pass (creating singleton modules).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/hierarchy/submod.cc

@@ -298,7 +298,7 @@ struct SubmodPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing SUBMOD pass (moving cells to submodules as requested).\n");
+		log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
 		log_push();
 
 		std::string opt_name;
@@ -321,7 +321,7 @@ struct SubmodPass : public Pass {
 		if (opt_name.empty())
 		{
 			Pass::call(design, "opt_clean");
-			log_header("Continuing SUBMOD pass.\n");
+			log_header(design, "Continuing SUBMOD pass.\n");
 
 			std::set<RTLIL::IdString> handled_modules;
 
@@ -356,7 +356,7 @@ struct SubmodPass : public Pass {
 				log("Nothing selected -> do nothing.\n");
 			else {
 				Pass::call_on_module(design, module, "opt_clean");
-				log_header("Continuing SUBMOD pass.\n");
+				log_header(design, "Continuing SUBMOD pass.\n");
 				SubmodWorker worker(design, module, copy_mode, opt_name);
 			}
 		}

passes/memory/memory.cc

@@ -53,7 +53,7 @@ struct MemoryPass : public Pass {
 		bool flag_nordff = false;
 		string memory_bram_opts;
 
-		log_header("Executing MEMORY pass.\n");
+		log_header(design, "Executing MEMORY pass.\n");
 		log_push();
 
 		size_t argidx;

passes/memory/memory_bram.cc

@@ -1211,7 +1211,7 @@ struct MemoryBramPass : public Pass {
 	{
 		rules_t rules;
 
-		log_header("Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
+		log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/memory/memory_collect.cc

@@ -247,7 +247,7 @@ struct MemoryCollectPass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
+		log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
 		extra_args(args, 1, design);
 		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))

passes/memory/memory_dff.cc

@@ -283,7 +283,7 @@ struct MemoryDffPass : public Pass {
 	{
 		bool flag_wr_only = false;
 
-		log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
+		log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/memory/memory_map.cc

@@ -363,7 +363,7 @@ struct MemoryMapPass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
+		log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
 		extra_args(args, 1, design);
 		for (auto mod : design->selected_modules())
 			MemoryMapWorker(design, mod);

passes/memory/memory_share.cc

@@ -747,7 +747,7 @@ struct MemorySharePass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
+		log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
 		extra_args(args, 1, design);
 		for (auto module : design->selected_modules())
 			MemoryShareWorker(design, module);

passes/memory/memory_unpack.cc

@@ -138,7 +138,7 @@ struct MemoryUnpackPass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
+		log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
 		extra_args(args, 1, design);
 		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))

passes/opt/opt.cc

@@ -71,7 +71,7 @@ struct OptPass : public Pass {
 		std::string opt_merge_args;
 		bool fast_mode = false;
 
-		log_header("Executing OPT pass (performing simple optimizations).\n");
+		log_header(design, "Executing OPT pass (performing simple optimizations).\n");
 		log_push();
 
 		size_t argidx;
@@ -132,7 +132,7 @@ struct OptPass : public Pass {
 				if (design->scratchpad_get_bool("opt.did_something") == false)
 					break;
 				Pass::call(design, "opt_clean" + opt_clean_args);
-				log_header("Rerunning OPT passes. (Removed registers in this run.)\n");
+				log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n");
 			}
 			Pass::call(design, "opt_clean" + opt_clean_args);
 		}
@@ -150,7 +150,7 @@ struct OptPass : public Pass {
 				Pass::call(design, "opt_expr" + opt_expr_args);
 				if (design->scratchpad_get_bool("opt.did_something") == false)
 					break;
-				log_header("Rerunning OPT passes. (Maybe there is more to do..)\n");
+				log_header(design, "Rerunning OPT passes. (Maybe there is more to do..)\n");
 			}
 		}
 
@@ -158,7 +158,7 @@ struct OptPass : public Pass {
 		design->sort();
 		design->check();
 
-		log_header(fast_mode ? "Finished fast OPT passes.\n" : "Finished OPT passes. (There is nothing left to do.)\n");
+		log_header(design, fast_mode ? "Finished fast OPT passes.\n" : "Finished OPT passes. (There is nothing left to do.)\n");
 		log_pop();
 	}
 } OptPass;

passes/opt/opt_clean.cc

@@ -380,7 +380,7 @@ struct OptCleanPass : public Pass {
 	{
 		bool purge_mode = false;
 
-		log_header("Executing OPT_CLEAN pass (remove unused cells and wires).\n");
+		log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
 		log_push();
 
 		size_t argidx;

passes/opt/opt_expr.cc

@@ -1151,7 +1151,7 @@ struct OptExprPass : public Pass {
 		bool do_fine = false;
 		bool keepdc = false;
 
-		log_header("Executing OPT_EXPR pass (perform const folding).\n");
+		log_header(design, "Executing OPT_EXPR pass (perform const folding).\n");
 		log_push();
 
 		size_t argidx;

passes/opt/opt_merge.cc

@@ -348,7 +348,7 @@ struct OptMergePass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing OPT_MERGE pass (detect identical cells).\n");
+		log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
 
 		bool mode_nomux = false;
 		bool mode_share_all = false;

passes/opt/opt_muxtree.cc

@@ -464,7 +464,7 @@ struct OptMuxtreePass : public Pass {
 	}
 	virtual void execute(vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
+		log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
 		extra_args(args, 1, design);
 
 		int total_count = 0;

passes/opt/opt_reduce.cc

@@ -354,7 +354,7 @@ struct OptReducePass : public Pass {
 	{
 		bool do_fine = false;
 
-		log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
+		log_header(design, "Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/opt/opt_rmdff.cc

@@ -191,7 +191,7 @@ struct OptRmdffPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		int total_count = 0;
-		log_header("Executing OPT_RMDFF pass (remove dff with constant values).\n");
+		log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
 
 		extra_args(args, 1, design);
 

passes/opt/share.cc

@@ -1500,7 +1500,7 @@ struct SharePass : public Pass {
 		config.generic_other_ops.insert("$alu");
 		config.generic_other_ops.insert("$macc");
 
-		log_header("Executing SHARE pass (SAT-based resource sharing).\n");
+		log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/opt/wreduce.cc

@@ -371,7 +371,7 @@ struct WreducePass : public Pass {
 	{
 		WreduceConfig config;
 
-		log_header("Executing WREDUCE pass (reducing word size of cells).\n");
+		log_header(design, "Executing WREDUCE pass (reducing word size of cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/proc/proc.cc

@@ -57,7 +57,7 @@ struct ProcPass : public Pass {
 	{
 		std::string global_arst;
 
-		log_header("Executing PROC pass (convert processes to netlists).\n");
+		log_header(design, "Executing PROC pass (convert processes to netlists).\n");
 		log_push();
 
 		size_t argidx;

passes/proc/proc_arst.cc

@@ -226,7 +226,7 @@ struct ProcArstPass : public Pass {
 		std::string global_arst;
 		bool global_arst_neg = false;
 
-		log_header("Executing PROC_ARST pass (detect async resets in processes).\n");
+		log_header(design, "Executing PROC_ARST pass (detect async resets in processes).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/proc/proc_clean.cc

@@ -156,7 +156,7 @@ struct ProcCleanPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		int total_count = 0;
-		log_header("Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
+		log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
 
 		extra_args(args, 1, design);
 

passes/proc/proc_dff.cc

@@ -369,7 +369,7 @@ struct ProcDffPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_DFF pass (convert process syncs to FFs).\n");
+		log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
 
 		extra_args(args, 1, design);
 

passes/proc/proc_dlatch.cc

@@ -292,7 +292,7 @@ struct ProcDlatchPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_DLATCH pass (convert process syncs to latches).\n");
+		log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n");
 
 		extra_args(args, 1, design);
 

passes/proc/proc_init.cc

@@ -100,7 +100,7 @@ struct ProcInitPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_INIT pass (extract init attributes).\n");
+		log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
 
 		extra_args(args, 1, design);
 

passes/proc/proc_mux.cc

@@ -391,7 +391,7 @@ struct ProcMuxPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
+		log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
 
 		extra_args(args, 1, design);
 

passes/proc/proc_rmdead.cc

@@ -76,7 +76,7 @@ struct ProcRmdeadPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
+		log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
 
 		extra_args(args, 1, design);
 

passes/sat/eval.cc

@@ -389,7 +389,7 @@ struct EvalPass : public Pass {
 		std::vector<std::string> shows, tables;
 		bool set_undef = false;
 
-		log_header("Executing EVAL pass (evaluate the circuit given an input).\n");
+		log_header(design, "Executing EVAL pass (evaluate the circuit given an input).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/sat/expose.cc

@@ -262,7 +262,7 @@ struct ExposePass : public Pass {
 		bool flag_evert_dff = false;
 		std::string sep = ".";
 
-		log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
+		log_header(design, "Executing EXPOSE pass (exposing internal signals as outputs).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/sat/freduce.cc

@@ -798,7 +798,7 @@ struct FreducePass : public Pass {
 		inv_mode = false;
 		dump_prefix = std::string();
 
-		log_header("Executing FREDUCE pass (perform functional reduction).\n");
+		log_header(design, "Executing FREDUCE pass (perform functional reduction).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/sat/miter.cc

@@ -32,7 +32,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	bool flag_make_assert = false;
 	bool flag_flatten = false;
 
-	log_header("Executing MITER pass (creating miter circuit).\n");
+	log_header(design, "Executing MITER pass (creating miter circuit).\n");
 
 	size_t argidx;
 	for (argidx = 2; argidx < args.size(); argidx++)
@@ -264,7 +264,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
 	bool flag_make_outputs = false;
 	bool flag_flatten = false;
 
-	log_header("Executing MITER pass (creating miter circuit).\n");
+	log_header(design, "Executing MITER pass (creating miter circuit).\n");
 
 	size_t argidx;
 	for (argidx = 2; argidx < args.size(); argidx++)

passes/sat/sat.cc

@@ -1073,7 +1073,7 @@ struct SatPass : public Pass {
 		int tempinduct_skip = 0, stepsize = 1;
 		std::string vcd_file_name, json_file_name, cnf_file_name;
 
-		log_header("Executing SAT pass (solving SAT problems in the circuit).\n");
+		log_header(design, "Executing SAT pass (solving SAT problems in the circuit).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/techmap/abc.cc

@@ -616,7 +616,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	if (!cleanup)
 		tempdir_name[0] = tempdir_name[4] = '_';
 	tempdir_name = make_temp_dir(tempdir_name);
-	log_header("Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
+	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
 			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
 
 	std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
@@ -834,7 +834,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 	if (count_output > 0)
 	{
-		log_header("Executing ABC.\n");
+		log_header(design, "Executing ABC.\n");
 
 		buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
 		f = fopen(buffer.c_str(), "wt");
@@ -904,7 +904,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 		ifs.close();
 
-		log_header("Re-integrating ABC results.\n");
+		log_header(design, "Re-integrating ABC results.\n");
 		RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
 		if (mapped_mod == NULL)
 			log_error("ABC output file does not contain a module `netlist'.\n");
@@ -1299,7 +1299,7 @@ struct AbcPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing ABC pass (technology mapping using ABC).\n");
+		log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
 		log_push();
 
 #ifdef ABCEXTERNAL
@@ -1599,7 +1599,7 @@ struct AbcPass : public Pass {
 					assigned_cells_reverse[cell] = key;
 				}
 
-				log_header("Summary of detected clock domains:\n");
+				log_header(design, "Summary of detected clock domains:\n");
 				for (auto &it : assigned_cells)
 					log("  %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
 							std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),

passes/techmap/aigmap.cc

@@ -41,7 +41,7 @@ struct AigmapPass : public Pass {
 	{
 		bool nand_mode = false;
 
-		log_header("Executing AIGMAP pass (map logic to AIG).\n");
+		log_header(design, "Executing AIGMAP pass (map logic to AIG).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/techmap/alumacc.cc

@@ -544,7 +544,7 @@ struct AlumaccPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing ALUMACC pass (create $alu and $macc cells).\n");
+		log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/techmap/dff2dffe.cc

@@ -285,7 +285,7 @@ struct Dff2dffePass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
+		log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
 
 		bool unmap_mode = false;
 		dict<IdString, IdString> direct_dict;

passes/techmap/dffinit.cc

@@ -41,7 +41,7 @@ struct DffinitPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFFINIT pass (set INIT param on FF cells).\n");
+		log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
 
 		dict<IdString, dict<IdString, IdString>> ff_types;
 

passes/techmap/dfflibmap.cc

@@ -547,7 +547,7 @@ struct DfflibmapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
+		log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
 
 		std::string liberty_file;
 		bool prepare_mode = false;

passes/techmap/dffsr2dff.cc

@@ -188,7 +188,7 @@ struct Dffsr2dffPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n");
+		log_header(design, "Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/techmap/extract.cc

@@ -442,7 +442,7 @@ struct ExtractPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing EXTRACT pass (map subcircuits to cells).\n");
+		log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n");
 		log_push();
 
 		SubCircuitSolver solver;
@@ -627,7 +627,7 @@ struct ExtractPass : public Pass {
 		std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
 		std::vector<RTLIL::Module*> needle_list;
 
-		log_header("Creating graphs for SubCircuit library.\n");
+		log_header(design, "Creating graphs for SubCircuit library.\n");
 
 		if (!mine_mode)
 			for (auto &mod_it : map->modules_) {
@@ -654,7 +654,7 @@ struct ExtractPass : public Pass {
 		if (!mine_mode)
 		{
 			std::vector<SubCircuit::Solver::Result> results;
-			log_header("Running solver from SubCircuit library.\n");
+			log_header(design, "Running solver from SubCircuit library.\n");
 
 			std::sort(needle_list.begin(), needle_list.end(), compareSortNeedleList);
 
@@ -667,7 +667,7 @@ struct ExtractPass : public Pass {
 
 			if (results.size() > 0)
 			{
-				log_header("Substitute SubCircuits with cells.\n");
+				log_header(design, "Substitute SubCircuits with cells.\n");
 
 				for (int i = 0; i < int(results.size()); i++) {
 					auto &result = results[i];
@@ -688,7 +688,7 @@ struct ExtractPass : public Pass {
 		{
 			std::vector<SubCircuit::Solver::MineResult> results;
 
-			log_header("Running miner from SubCircuit library.\n");
+			log_header(design, "Running miner from SubCircuit library.\n");
 			solver.mine(results, mine_cells_min, mine_cells_max, mine_min_freq, mine_limit_mod);
 
 			map = new RTLIL::Design;

passes/techmap/hilomap.cc

@@ -76,7 +76,7 @@ struct HilomapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing HILOMAP pass (mapping to constant drivers).\n");
+		log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n");
 
 		hicell_celltype = std::string();
 		hicell_portname = std::string();

passes/techmap/iopadmap.cc

@@ -68,7 +68,7 @@ struct IopadmapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
+		log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
 
 		std::string inpad_celltype, inpad_portname, inpad_portname2;
 		std::string outpad_celltype, outpad_portname, outpad_portname2;

passes/techmap/lut2mux.cc

@@ -67,7 +67,7 @@ struct Lut2muxPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
+		log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/techmap/maccmap.cc

@@ -379,7 +379,7 @@ struct MaccmapPass : public Pass {
 	{
 		bool unmap_mode = false;
 
-		log_header("Executing MACCMAP pass (map $macc cells).\n");
+		log_header(design, "Executing MACCMAP pass (map $macc cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/techmap/muxcover.cc

@@ -581,7 +581,7 @@ struct MuxcoverPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing MUXCOVER pass (mapping to wider MUXes).\n");
+		log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n");
 
 		bool use_mux4 = false;
 		bool use_mux8 = false;

passes/techmap/nlutmap.cc

@@ -143,7 +143,7 @@ struct NlutmapPass : public Pass {
 	{
 		NlutmapConfig config;
 
-		log_header("Executing NLUTMAP pass (mapping to constant drivers).\n");
+		log_header(design, "Executing NLUTMAP pass (mapping to constant drivers).\n");
 		log_push();
 
 		size_t argidx;

passes/techmap/pmuxtree.cc

@@ -78,7 +78,7 @@ struct PmuxtreePass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PMUXTREE pass.\n");
+		log_header(design, "Executing PMUXTREE pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/techmap/shregmap.cc

@@ -360,7 +360,7 @@ struct ShregmapPass : public Pass {
 		ShregmapOptions opts;
 		string clkpol, enpol;
 
-		log_header("Executing SHREGMAP pass (map shift registers).\n");
+		log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

passes/techmap/simplemap.cc

@@ -543,7 +543,7 @@ struct SimplemapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
+		log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
 		extra_args(args, 1, design);
 
 		std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;

passes/techmap/techmap.cc

@@ -779,7 +779,7 @@ struct TechmapWorker
 
 					if (recursive_mode) {
 						if (log_continue) {
-							log_header("Continuing TECHMAP pass.\n");
+							log_header(design, "Continuing TECHMAP pass.\n");
 							log_continue = false;
 						}
 						while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
@@ -790,7 +790,7 @@ struct TechmapWorker
 					continue;
 
 				if (log_continue) {
-					log_header("Continuing TECHMAP pass.\n");
+					log_header(design, "Continuing TECHMAP pass.\n");
 					log_continue = false;
 				}
 
@@ -833,7 +833,7 @@ struct TechmapWorker
 		}
 
 		if (log_continue) {
-			log_header("Continuing TECHMAP pass.\n");
+			log_header(design, "Continuing TECHMAP pass.\n");
 			log_continue = false;
 		}
 
@@ -976,7 +976,7 @@ struct TechmapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing TECHMAP pass (map to technology primitives).\n");
+		log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
 		log_push();
 
 		TechmapWorker worker;
@@ -1108,7 +1108,7 @@ struct FlattenPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FLATTEN pass (flatten design).\n");
+		log_header(design, "Executing FLATTEN pass (flatten design).\n");
 		log_push();
 
 		extra_args(args, 1, design);

passes/techmap/tribuf.cc

@@ -160,7 +160,7 @@ struct TribufPass : public Pass {
 	{
 		TribufConfig config;
 
-		log_header("Executing TRIBUF pass.\n");
+		log_header(design, "Executing TRIBUF pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {

passes/tests/test_autotb.cc

@@ -333,7 +333,7 @@ struct TestAutotbBackend : public Backend {
 	{
 		int num_iter = 1000;
 
-		log_header("Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n");
+		log_header(design, "Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n");
 
 		int argidx;
 		for (argidx = 1; argidx < GetSize(args); argidx++)