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Author	SHA1	Message	Date
Eddie Hung	bae3d8705d	Update comments in abc9_map.v	2019-10-07 12:54:45 -07:00
Eddie Hung	1dc22607c3	Remove -D_ABC9	2019-10-07 12:21:52 -07:00
Eddie Hung	1504ca2cd9	Remove "write_xaiger -zinit"	2019-10-07 11:58:49 -07:00
Eddie Hung	e1554b56dd	Add comment on default flop init	2019-10-07 11:56:17 -07:00
Eddie Hung	d9fba95177	Get rid of output_port lookup	2019-10-07 11:49:06 -07:00
Clifford Wolf	4072a96663	Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry ... Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf	2019-10-06 12:11:20 +02:00
Eddie Hung	3879ca1398	Do not require changes to cells_sim.v; try and work out comb model	2019-10-05 22:55:18 -07:00
Eddie Hung	5c68da4150	Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf	2019-10-05 09:27:12 -07:00
Clifford Wolf	10d0bad67e	Update README.md	2019-10-05 18:13:04 +02:00
Eddie Hung	3c6e5d82a6	Error if $currQ not found	2019-10-05 09:06:13 -07:00
Eddie Hung	f90a4b1e24	Missed this	2019-10-05 08:57:37 -07:00
Eddie Hung	991c2ca95b	Add comment on why we have to match for clock-enable/reset muxes	2019-10-05 08:56:37 -07:00
Eddie Hung	ebb059896a	Add note on pattern detector	2019-10-05 08:53:01 -07:00
Miodrag Milanović	7c074ef844	Merge pull request #1436 from YosysHQ/mmicko/msvc_fix ... Fixes for MSVC build	2019-10-05 07:48:30 +02:00
Eddie Hung	6c5e1234e1	Add comment on why partial multipliers are 18x18	2019-10-04 22:31:04 -07:00
Eddie Hung	792cd31052	Add comments for xilinx_dsp_cascade	2019-10-04 22:31:04 -07:00
Eddie Hung	12fd2ec4f0	Improve comments for xilinx_dsp_CREG	2019-10-04 22:31:04 -07:00
Eddie Hung	14e4aeece6	Fix comment	2019-10-04 22:31:04 -07:00
Eddie Hung	8027ebf05b	Restore optimisation for sigM.empty()	2019-10-04 22:31:04 -07:00
Eddie Hung	77d7a5c14a	Retry on fixing TODOs	2019-10-04 22:31:04 -07:00
Eddie Hung	52583ecff8	Revert "Fix TODOs" ... This reverts commit 8674a6c68d563908014d16671567459499c6dc99.	2019-10-04 22:31:04 -07:00
Eddie Hung	6d68972619	More comments, cleanup	2019-10-04 22:31:04 -07:00
Eddie Hung	7de9c33931	Fix TODOs	2019-10-04 22:31:04 -07:00
Eddie Hung	983068103e	Consistency	2019-10-04 22:31:04 -07:00
Eddie Hung	cf82b38478	Add comments for xilinx_dsp	2019-10-04 22:31:04 -07:00
Eddie Hung	b47bb5c810	Fix typo in check_label()	2019-10-04 21:43:50 -07:00
Eddie Hung	a2ef93f03a	abc -> abc9	2019-10-04 17:56:38 -07:00
Eddie Hung	a5ac33f230	Merge branch 'master' into eddie/abc_to_abc9	2019-10-04 17:53:20 -07:00
Eddie Hung	f0cadb0de8	Fix from merge	2019-10-04 17:52:19 -07:00
Eddie Hung	bbc0e06af3	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-10-04 17:39:08 -07:00
Eddie Hung	0acc51c3d8	Add temporary abc9 -nomfs and use for synth_xilinx -abc9	2019-10-04 17:35:43 -07:00
Eddie Hung	d4212d128b	Use read_args for read_verilog	2019-10-04 17:27:05 -07:00
Eddie Hung	9c23811839	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
Eddie Hung	7959e9d6b2	Fix merge issues	2019-10-04 17:21:14 -07:00
Eddie Hung	7a45cd5856	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
Eddie Hung	74ef8feeaf	Fix xilinx_dsp for unsigned extensions	2019-10-04 16:46:15 -07:00
Eddie Hung	6bf7114bbd	Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again	2019-10-04 16:45:36 -07:00
Eddie Hung	279fd22ddf	Add Const::{begin,end,empty}()	2019-10-04 15:00:57 -07:00
Eddie Hung	aae2b9fd9c	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
Eddie Hung	9fef1df3c1	Panic over. Model was elsewhere. Re-arrange for consistency	2019-10-04 10:48:44 -07:00
Eddie Hung	4e11782cde	Oops	2019-10-04 10:36:02 -07:00
Eddie Hung	c0f54d3fd5	Ohmilord this wasn't added all this time!?!	2019-10-04 10:34:16 -07:00
Eddie Hung	84f978bdc2	Add -async2sync to help text as per @daveshah1	2019-10-04 10:17:46 -07:00
Miodrag Milanovic	c0b14cfea7	Fixes for MSVC build	2019-10-04 16:29:46 +02:00
Miodrag Milanovic	44c3472b9f	FF should be initialized to 0	2019-10-04 13:27:10 +02:00
Miodrag Milanovic	c0fa6f3e1a	Split mux tests per type	2019-10-04 13:05:16 +02:00
Miodrag Milanovic	1b80489486	Split latch check	2019-10-04 13:00:09 +02:00
Miodrag Milanovic	77d557d00b	Add missing latch mapping	2019-10-04 12:58:11 +02:00
Miodrag Milanovic	2c3e140246	split rest od ff's	2019-10-04 12:51:45 +02:00
Miodrag Milanovic	3de7889d08	Separate check for ff's types	2019-10-04 12:48:27 +02:00