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4358 commits

Author SHA1 Message Date
Eddie Hung
5a0a5aae4f Compile abc9 2019-02-08 13:58:47 -08:00
Eddie Hung
edf7267019 Refactor kernel/cost.h definition into cost.cc 2019-02-08 13:58:20 -08:00
Eddie Hung
e25a22015f Copy abc.cc to abc9.cc 2019-02-08 13:23:54 -08:00
Eddie Hung
8886fa5506 addDff -> addDffGate as per @daveshah1 2019-02-08 13:17:53 -08:00
Eddie Hung
afc3c4b613 Fix tabulation 2019-02-08 13:17:02 -08:00
Eddie Hung
aa66d8f12f -module_name arg to go before -clk_name 2019-02-08 12:49:55 -08:00
Eddie Hung
587872236e Support and differentiate between ASCII and binary AIG testing 2019-02-08 12:41:59 -08:00
Eddie Hung
391ec75b07 Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
Eddie Hung
fb8ad440a3 Allow module name to be determined by argument too 2019-02-08 12:40:43 -08:00
Eddie Hung
f1befe1b44 Refactor into AigerReader class 2019-02-08 12:04:26 -08:00
Eddie Hung
2a8cc36578 Parse binary AIG files 2019-02-08 11:45:16 -08:00
Eddie Hung
4e6c5e4672 Add binary AIGs converted from AAG 2019-02-08 11:41:25 -08:00
Eddie Hung
09d758f0a3 Refactor to parse_aiger_header() 2019-02-08 10:54:31 -08:00
Eddie Hung
36c56bf412 Add comment 2019-02-08 08:37:44 -08:00
Eddie Hung
5e24251a61 Handle reset logic in latches 2019-02-08 08:37:18 -08:00
Eddie Hung
652e414392 Change literal vars from int to unsigned 2019-02-08 08:09:30 -08:00
Eddie Hung
fafa972238 Create clk outside of latch loop 2019-02-08 08:08:49 -08:00
Eddie Hung
02f603ac1a Handle latch symbols too 2019-02-08 08:05:27 -08:00
Eddie Hung
5a593ff41c Remove return after log_error 2019-02-08 08:04:48 -08:00
Eddie Hung
6dbeda1807 Add support for symbol tables 2019-02-08 08:03:40 -08:00
Eddie Hung
791f93181d Stub for binary AIGER 2019-02-08 07:31:04 -08:00
Eddie Hung
40db2f2eb6 Refactor 2019-02-06 14:58:47 -08:00
Eddie Hung
4167b15de5 Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig 2019-02-06 14:31:11 -08:00
Eddie Hung
3f87cf86cc Revert most of autotest.sh; for non *.v use Yosys to translate 2019-02-06 14:30:19 -08:00
Eddie Hung
c373640a3a Refactor 2019-02-06 14:28:44 -08:00
Eddie Hung
8241db6960 write_verilog to cope with init attr on q when -noexpr 2019-02-06 14:17:09 -08:00
Eddie Hung
742b4e01b4 Add INIT parameter to all ff/latch cells 2019-02-06 14:16:26 -08:00
Eddie Hung
115883f467 Add tests for simple cases using defparam 2019-02-06 14:15:17 -08:00
Eddie Hung
281f2aadca Add -B option to autotest.sh to append to backend_opts 2019-02-06 14:14:55 -08:00
Eddie Hung
03cf1532a7 Extend testcase 2019-02-06 14:02:11 -08:00
Eddie Hung
a9674bd2ec Add testcase 2019-02-06 12:49:30 -08:00
Eddie Hung
fdd55d064b Rename ASCII tests 2019-02-06 12:20:36 -08:00
Eddie Hung
cc0b723484 WIP 2019-02-06 12:19:48 -08:00
Clifford Wolf
e112d2fbf5 Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-06 16:35:59 +01:00
Eddie Hung
3f0bb441f8 Add tests 2019-02-04 16:46:24 -08:00
Clifford Wolf
266511b29e
Merge pull request #798 from mmicko/master
Fixed Anlogic simulation model
2019-01-27 09:25:18 +01:00
Clifford Wolf
81581f24fc
Merge pull request #800 from whitequark/write_verilog_tribuf
write_verilog: write $tribuf cell as ternary
2019-01-27 09:23:41 +01:00
Clifford Wolf
bf798a9020 Merge branch 'whitequark-write_verilog_keyword' 2019-01-27 09:17:29 +01:00
Clifford Wolf
9666cca9dd Remove asicworld tests for (unsupported) switch-level modelling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-27 09:17:02 +01:00
whitequark
3d7925ad9f write_verilog: write $tribuf cell as ternary. 2019-01-27 00:24:06 +00:00
whitequark
42c47a83da write_verilog: escape names that match SystemVerilog keywords. 2019-01-27 00:03:53 +00:00
David Shah
c82aa49d9e
Merge pull request #796 from whitequark/proc_clean_typo
proc_clean: fix critical typo
2019-01-25 21:33:06 +00:00
Miodrag Milanovic
0de328da8f Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
whitequark
58d059ccb7 proc_clean: fix critical typo. 2019-01-23 22:08:38 +00:00
Clifford Wolf
c4b61f2d69
Merge pull request #793 from whitequark/proc_clean_fix_fully_def
proc_clean: fix fully def check to consider compare/signal length
2019-01-19 09:31:17 +01:00
whitequark
95b6c35882 proc_clean: fix fully def check to consider compare/signal length.
Fixes #790.
2019-01-18 23:22:19 +00:00
Clifford Wolf
f3556e9f7a Cleanups in igloo2 example design
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 14:54:04 +01:00
Clifford Wolf
db5765b443 Add SF2 IO buffer insertion
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 14:38:37 +01:00
Clifford Wolf
9b277fc21e Improve Igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 13:35:52 +01:00
Clifford Wolf
841ca74c90 Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 13:33:45 +01:00