mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-08 18:31:51 +00:00
Code Activity

Change literal vars from int to unsigned

Browse source
This commit is contained in:
Eddie Hung 2019-02-08 08:09:30 -08:00
parent fafa972238
commit 652e414392
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
frontends/aiger/aigerparse.cc
View file

@ -100,7 +100,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
return wire;
};
int l1, l2, l3;
unsigned l1, l2, l3;
// Parse inputs
std::vector<RTLIL::Wire*> inputs;