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Author SHA1 Message Date
Miodrag Milanovic
5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf fix yosys path 2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675 Fix path to yosys 2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1 Add async2sync 2019-10-18 11:00:27 +02:00
Miodrag Milanović
0568920d79
Merge pull request #1435 from YosysHQ/mmicko/efinix 
Add tests for Efinix architecture (contd)
 2019-10-18 10:54:35 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix 2019-10-18 10:54:28 +02:00
Miodrag Milanović
ab4899a2d0
Merge pull request #1434 from YosysHQ/mmicko/anlogic 
Add tests for Anlogic architecture (contd)
 2019-10-18 10:54:04 +02:00
Miodrag Milanović
66fca65b58
Merge branch 'master' into mmicko/anlogic 2019-10-18 10:53:56 +02:00
Miodrag Milanović
5ffb0053ec
Merge pull request #1421 from YosysHQ/eddie/pr1352 
Add tests for ECP5 architecture (contd)
 2019-10-18 10:53:34 +02:00
Miodrag Milanović
0b0b0cc0d9
Merge branch 'master' into eddie/pr1352 2019-10-18 10:52:50 +02:00
Miodrag Milanović
e0a67fce12
Merge pull request #1420 from YosysHQ/eddie/pr1363 
Add tests for Xilinx architecture (contd)
 2019-10-18 10:51:32 +02:00
Miodrag Milanovic
b659082e4a hierarchy - proc reorder 2019-10-18 09:13:06 +02:00
Miodrag Milanovic
46af9a0ff7 hierarchy - proc reorder 2019-10-18 09:06:43 +02:00
Miodrag Milanovic
0d60902fd9 hierarchy - proc reorder 2019-10-18 09:04:02 +02:00
Miodrag Milanovic
e6ad714d20 hierarchy - proc reorder 2019-10-18 08:06:57 +02:00
Miodrag Milanovic
980df499ab Make equivalence work with latest master 2019-10-17 17:24:53 +02:00
Miodrag Milanovic
b2f0d75807 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
1a399c6456 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
a198bcdd4f split muxes synth per type 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
36af102801 Test dffs separetely 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
487b38b124 Split latches into separete tests 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718 Fix formatting 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90 Clean verilog code from not used define block 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
d37cd267a5 Removed alu and div_mod test as agreed, ignore generated files 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
a7fbc8c3fe Test per flip-flop type 2019-10-17 17:10:42 +02:00
Eddie Hung
3b44084320 Add -assert 2019-10-17 17:10:42 +02:00
Eddie Hung
8422ad3e3a Use built-in async2sync call as per #1417 2019-10-17 17:10:42 +02:00
Eddie Hung
5b7bc3ab85 Update mul test to DSP48E1 2019-10-17 17:10:02 +02:00
Eddie Hung
08bd1816e3 Update area for div_mod 2019-10-17 17:10:02 +02:00
Eddie Hung
a12801843b Add comment for lack of tristate logic pointing to #1225 2019-10-17 17:10:02 +02:00
Eddie Hung
eded90b6b4 Move $x to end as 7f0eec8 2019-10-17 17:10:02 +02:00
SergeyDegtyar
305672170b adffs test update (equiv_opt -multiclock) 2019-10-17 17:10:02 +02:00
Sergey
bb70eb977d Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
68f9239c57 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
df6d0b95da Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
c340d54657 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
205f52ffe5 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
df7fe40529 Fix div_mod test 2019-10-17 17:10:02 +02:00
SergeyDegtyar
7bc8f0c2e2 Add comment with expected behavior for latches,tribuf tests;Update adffs test 2019-10-17 17:10:02 +02:00
SergeyDegtyar
489444bcba Fix latches.ys test 2019-10-17 17:10:02 +02:00
SergeyDegtyar
6331fa5b02 Remove xilinx_ug901 tests (will be moved to yosys-tests) 2019-10-17 17:10:02 +02:00
SergeyDegtyar
757c476f62 Add smoke tests to tests/xilinx 2019-10-17 17:10:02 +02:00
SergeyDegtyar
ca7a58bcc8 Add comments for unproven cells. 2019-10-17 17:08:38 +02:00
SergeyDegtyar
2ae7dec530 Add tests for Xilinx UG901 examples 2019-10-17 17:08:38 +02:00
Clifford Wolf
0d037bf9d8
Merge pull request #1450 from YosysHQ/clifford/fixdffmux 
Fix handling of init attributes in peepopt dffmux pattern
 2019-10-16 14:44:38 +02:00
Clifford Wolf
b8774ae849 Fix dffmux peepopt init handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5 Move GENERATE_PATTERN macro to separate utility header 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441 Disable left-over log_debug in peepopt_dffmux.pmg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 10:43:47 +02:00
Clifford Wolf
71936209cf Fix parsing of .cname BLIF statements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 09:06:57 +02:00