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Author	SHA1	Message	Date
Clifford Wolf	55bf8f69e0	Fix port hanlding in pmgen ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:26:54 +02:00
Clifford Wolf	adb81ba386	Add pmgen slices and choices ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:15:50 +02:00
Eddie Hung	fe1b2337fd	Do not propagate mem2reg attribute through to result	2019-08-22 16:57:59 -07:00
Eddie Hung	c50d68653d	Spelling	2019-08-22 16:06:36 -07:00
Eddie Hung	2fe35f902b	Merge pull request #1322 from mmicko/pyosys_osx ... do not require boost if pyosys is not used	2019-08-22 11:53:27 -07:00
Miodrag Milanovic	e5dac8096d	do not require boost if pyosys is not used	2019-08-22 20:43:52 +02:00
Eddie Hung	926cd10350	Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk ... require tcl-tk in Brewfile	2019-08-22 11:32:44 -07:00
Eddie Hung	b800059fc1	Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx ... opt_expr to trim A port of $shiftx/$shift	2019-08-22 10:31:27 -07:00
Clifford Wolf	e9f3eb9760	Bump year in copyright notice ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:43:16 +02:00
Clifford Wolf	151db528e4	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:09:37 +02:00
Clifford Wolf	2c8c8b3c74	Merge pull request #1289 from mmicko/anlogic_fixes ... Anlogic fixes and optimization	2019-08-22 18:09:10 +02:00
Clifford Wolf	4c449caf9b	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:06:36 +02:00
Clifford Wolf	4d37710e82	Merge pull request #1281 from mmicko/efinix ... Initial support for Efinix Trion series FPGAs	2019-08-22 18:06:02 +02:00
Eddie Hung	9245f0d3f5	Copy-paste typo	2019-08-22 08:43:44 -07:00
Chris Shucksmith	d0322e9584	require tcl-tk in Brewfile	2019-08-22 16:37:40 +01:00
Eddie Hung	6f971470f8	Respect opt_expr -keepdc as per @cliffordwolf	2019-08-22 08:37:27 -07:00
Eddie Hung	379f33af54	Handle $shift and Y_WIDTH > 1 as per @cliffordwolf	2019-08-22 08:22:23 -07:00
Eddie Hung	9e31f01b34	Add cover()	2019-08-22 08:06:24 -07:00
Eddie Hung	d0ffe7544c	Canonical form	2019-08-22 08:05:01 -07:00
Clifford Wolf	34a7c0209d	Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg ... mem2reg to preserve user attributes and src	2019-08-22 10:24:42 +02:00
Eddie Hung	bb1a8a0190	Add test	2019-08-21 21:58:20 -07:00
Eddie Hung	d3a212ff91	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 21:53:55 -07:00
whitequark	841903582f	Merge pull request #1315 from mmicko/fix_dependencies ... Fix test_pmgen deps	2019-08-21 21:40:31 +00:00
Eddie Hung	a6776ee35e	mem2reg to preserve user attributes and src	2019-08-21 13:36:01 -07:00
Miodrag Milanovic	948b6f91a1	Fix test_pmgen deps	2019-08-21 17:00:24 +02:00
Clifford Wolf	7d8db1c053	Merge pull request #1314 from YosysHQ/eddie/fix_techmap ... techmap -max_iter to apply to each module individually	2019-08-21 09:12:56 +02:00
Eddie Hung	076af2e617	Missing newline	2019-08-20 20:37:52 -07:00
Eddie Hung	9b9d759451	Fix copy-paste typo	2019-08-20 20:18:51 -07:00
Eddie Hung	fe61dcce8b	Grammar	2019-08-20 20:05:51 -07:00
Eddie Hung	fce8dc7db2	Add test	2019-08-20 20:05:16 -07:00
Eddie Hung	193eae0c84	techmap -max_iter to apply to each module individually	2019-08-20 19:50:20 -07:00
Eddie Hung	33960dd3d8	Merge pull request #1209 from YosysHQ/eddie/synth_xilinx ... [WIP] synth xilinx renaming, as per #1184	2019-08-20 12:55:26 -07:00
Eddie Hung	14c03861b6	Merge pull request #1304 from YosysHQ/eddie/abc9_refactor ... Refactor abc9 to use port attributes, not module attributes	2019-08-20 11:59:31 -07:00
Eddie Hung	d9fe4cccbf	Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx	2019-08-20 11:57:52 -07:00
Clifford Wolf	ba71e4f8f2	Merge pull request #1298 from YosysHQ/clifford/pmgen ... Improvements in pmgen	2019-08-20 11:39:42 +02:00
Clifford Wolf	d0117d7d12	Merge branch 'master' into clifford/pmgen	2019-08-20 11:39:23 +02:00
Clifford Wolf	6ffb910d12	Add test case for real parameters ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-20 11:38:21 +02:00
Clifford Wolf	c25c1e742b	Merge pull request #1308 from jakobwenzel/real_params ... Handle real values when deriving ast modules	2019-08-20 11:37:26 +02:00
whitequark	749ff864aa	Merge pull request #1309 from whitequark/proc_clean-fix-1268 ... proc_clean: fix order of switch insertion	2019-08-20 00:45:41 +00:00
Eddie Hung	3f4886e7a3	Fix typo	2019-08-19 10:42:00 -07:00
Eddie Hung	7e010834eb	Fix typo	2019-08-19 10:41:18 -07:00
Eddie Hung	f42ba811b6	ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc	2019-08-19 10:11:47 -07:00
Eddie Hung	29e4c8bd06	Clarify with 'only'	2019-08-19 10:00:53 -07:00
Eddie Hung	c36fca86f7	Update doc	2019-08-19 09:59:57 -07:00
Eddie Hung	d81a090d89	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
whitequark	4a942ba7b9	proc_clean: fix order of switch insertion. ... Fixes #1268.	2019-08-19 16:44:23 +00:00
Jakob Wenzel	24971fda87	handle real values when deriving ast modules	2019-08-19 14:17:36 +02:00
Clifford Wolf	4adcbecec5	Merge pull request #1306 from mmicko/gitignore_fix ... Ignore all generated headers for pmgen pass	2019-08-19 13:09:12 +02:00
Clifford Wolf	21699e5840	Add *.sv to tests/simple_abc9/.gitignore ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-19 13:04:57 +02:00
Clifford Wolf	1e3dd0a2da	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen	2019-08-19 13:04:06 +02:00