429 commits

Author	SHA1	Message	Date
Eddie Hung	5562cb08a4	Use single DSP_SIGNEDONLY macro	2019-07-18 13:09:55 -07:00
Eddie Hung	e3f8e59f18	Make all operands signed	2019-07-17 14:25:40 -07:00
Eddie Hung	58e63feae1	Update comment	2019-07-17 13:26:17 -07:00
Eddie Hung	c501aa5ee8	Signedness	2019-07-16 15:54:27 -07:00
Eddie Hung	6390c535ba	Revert drop down to 24x16 multipliers for all	2019-07-16 14:30:25 -07:00
Eddie Hung	569cd66764	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	2019-07-16 14:18:36 -07:00
Eddie Hung	5d1ce04381	Add support for {A,B,P}REG in DSP48E1	2019-07-16 14:05:50 -07:00
David Shah	d38df68d26	xilinx: Add correct signed behaviour to DSP48E1 model ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 17:53:08 +01:00
David Shah	95c8d27b0b	xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 16:47:53 +01:00
Eddie Hung	5f00d335d4	Oops forgot these files	2019-07-15 15:03:15 -07:00
Eddie Hung	0c7ee6d0fa	Move DSP mapping back out to dsp_map.v	2019-07-15 14:18:44 -07:00
Eddie Hung	20e3d2d9b0	Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim	2019-07-15 11:13:22 -07:00
Eddie Hung	146451a767	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-07-15 09:49:41 -07:00
Eddie Hung	19c1c3cfa3	Merge pull request #1182 from koriakin/xc6s-bram ... synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 12:55:35 -07:00
Marcin Kościelnicki	a9efacd01d	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Eddie Hung	b33ecd2a74	Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little	2019-07-10 16:00:03 -07:00
Eddie Hung	cea7441d8a	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-07-10 15:58:01 -07:00
Eddie Hung	bb2144ae73	Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime ... Error out if -abc9 and -retime specified	2019-07-10 14:38:13 -07:00
Eddie Hung	6bbd286e03	Error out if -abc9 and -retime specified	2019-07-10 12:47:48 -07:00
Eddie Hung	58bb84e5b2	Add some spacing	2019-07-10 12:32:33 -07:00
Eddie Hung	521971e32e	Add some ASCII art explaining mux decomposition	2019-07-10 12:20:04 -07:00
Eddie Hung	e573d024a2	Call muxpack and pmux2shiftx before cmp2lut	2019-07-09 21:26:38 -07:00
Eddie Hung	c55530b901	Restore opt_clean back to original place	2019-07-09 14:29:58 -07:00
Eddie Hung	5b48b18d29	Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6	2019-07-09 14:28:54 -07:00
Eddie Hung	b1a048a703	Extend using A[1] to preserve don't care	2019-07-09 12:35:41 -07:00
Eddie Hung	93522b0ae1	Extend during mux decomposition with 1'bx	2019-07-09 10:59:37 -07:00
Eddie Hung	c864995343	Fix typo and comments	2019-07-09 10:38:07 -07:00
Eddie Hung	c91cb73562	Merge remote-tracking branch 'origin/master' into xc7mux	2019-07-09 10:22:49 -07:00
Eddie Hung	c68b909210	synth_xilinx to call commands of synth -coarse directly	2019-07-09 10:21:54 -07:00
Eddie Hung	737340327f	Revert "synth_xilinx to call "synth -run coarse" with "-keepdc"" ... This reverts commit 7f964859ec.	2019-07-09 10:15:02 -07:00
Eddie Hung	bc84f7dd10	Fix spacing	2019-07-09 09:22:12 -07:00
Eddie Hung	667199d460	Fix spacing	2019-07-09 09:16:00 -07:00
Eddie Hung	6951e32070	Decompose mux inputs in delay-orientated (rather than area) fashion	2019-07-08 23:51:13 -07:00
Eddie Hung	45da3ada7b	Do not call opt -mux_undef (part of -full) before muxcover	2019-07-08 23:49:16 -07:00
Eddie Hung	d4ab43d940	Add one more comment	2019-07-08 23:05:48 -07:00
Eddie Hung	939a225f92	Less thinking	2019-07-08 23:02:57 -07:00
Eddie Hung	de40453553	Reword	2019-07-08 22:56:19 -07:00
Eddie Hung	7f964859ec	synth_xilinx to call "synth -run coarse" with "-keepdc"	2019-07-08 19:23:24 -07:00
Eddie Hung	3f86407cc3	Map $__XILINX_SHIFTX in a more balanced manner	2019-07-08 17:06:35 -07:00
Eddie Hung	78914e2e0e	Capitalisation	2019-07-08 17:06:22 -07:00
Eddie Hung	baf47e496f	Add synth_xilinx -widemux recommended value	2019-07-08 17:04:39 -07:00
Eddie Hung	895ca50173	Fixes for 2:1 muxes	2019-07-08 12:03:38 -07:00
Eddie Hung	0944acf3af	synth_xilinx -widemux=2 is minimum now	2019-07-08 11:29:21 -07:00
David Shah	c865559f95	xc7: Map combinational DSP48E1s ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-08 19:15:25 +01:00
Eddie Hung	dbe1326573	Parametric muxcover costs as per @daveshah1	2019-07-08 11:08:20 -07:00
Eddie Hung	c58998a7d2	atoi -> stoi as per @daveshah1	2019-07-08 10:48:10 -07:00
Eddie Hung	810f8c5dbd	Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup	2019-07-02 09:21:02 -07:00
Eddie Hung	2ea6083b7e	Fix $__XILINX_MUXF78 box timing	2019-07-01 14:04:06 -07:00
Eddie Hung	09ac274716	Revert "Fix broken MUXFx box, use MUXF7x2 box instead" ... This reverts commit a9a140aa6c.	2019-07-01 14:01:09 -07:00