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Code Activity
5607 commits 122 branches 59 tags 73 MiB
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969 commits

Author SHA1 Message Date
Eddie Hung
5a46a0b385 Fine tune aigerparse 2019-06-07 16:57:32 -07:00
Eddie Hung
1e201a9b01 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-07 16:15:19 -07:00
Eddie Hung
2b350401c4 Fix spacing from spaces to tabs 2019-06-07 15:44:57 -07:00
Eddie Hung
6934f4bdd5 Fix spacing (entire file is wrong anyway, will fix later) 2019-06-07 11:30:36 -07:00
Eddie Hung
d00ae1d6a8 Remove unnecessary std::getline() for ASCII 2019-06-07 11:28:25 -07:00
Eddie Hung
a04521c6b7 Fix read_aiger -- create zero driver, fix init width, parse 'b' 2019-06-07 11:07:15 -07:00
Clifford Wolf
211d85cfcc Fixes and cleanups in AST_TECALL handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 12:41:09 +02:00
Clifford Wolf
a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf
a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
Eddie Hung
eaee250a6e Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:06:59 -07:00
tux3
88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Clifford Wolf
b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn 
Added support for parsing attributes on port connections.
 2019-06-06 12:34:05 +02:00
Maciej Kurc
03e0d3a17c Fixed memory leak. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-05 10:42:43 +02:00
Eddie Hung
f81a0ed92e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-03 23:07:08 -07:00
Eddie Hung
d018cd9fe3 Assert that box_unique_id is indeed unique 2019-06-03 12:33:47 -07:00
Eddie Hung
a54822b1bc Skip internal modules when generating box_unique_id 2019-06-03 12:31:23 -07:00
Clifford Wolf
36120fcc30 Only support Symbiotic EDA flavored Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-02 10:14:50 +02:00
Eddie Hung
e3d160a9ca parse_xaiger to cope with flops 2019-05-31 18:06:36 -07:00
Eddie Hung
eb08e71bd1 Merge branch 'xaig' into xc7mux 2019-05-31 13:03:03 -07:00
Maciej Kurc
a6cadf6318 Added support for parsing attributes on port connections. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-31 14:58:43 +02:00
Eddie Hung
a41553a861 read_xaiger() to name box signals 2019-05-30 16:02:40 -07:00
Eddie Hung
c6fa4faa37 Remove whitespace 2019-05-30 12:25:21 -07:00
Eddie Hung
fdfc18be91 Carry in/out to be the last input/output for chains to be preserved 2019-05-30 01:23:36 -07:00
Clifford Wolf
2faa1d0e80 Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-30 10:04:26 +02:00
Eddie Hung
ba9513b325 Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-28 09:30:53 -07:00
Eddie Hung
f745727de5 read_aiger to only clean own design 2019-05-28 08:45:10 -07:00
Eddie Hung
3eec100748 Parse "a" extension and boxes from map file 2019-05-27 23:11:21 -07:00
Eddie Hung
428d7c8e11 Remove unused function 2019-05-27 13:49:42 -07:00
Eddie Hung
e115e736fa parse_xaiger to not parse symbol table 2019-05-27 12:34:17 -07:00
Eddie Hung
234156c01a Instantiate cell type (from sym file) otherwise 'clean' warnings 2019-05-27 12:16:10 -07:00
Eddie Hung
03b289a851 Add 'cinput' and 'coutput' to symbols file for boxes 2019-05-27 11:38:52 -07:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel
cd12f2ddcf remove leftovers from ast data structures 2019-05-27 18:01:44 +02:00
Stefan Biereigel
ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf
92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range 
Give error instead of asserting for invalid range, fixes #947
 2019-05-27 13:26:12 +02:00
Miodrag Milanovic
84ffb21708 Give error instead of asserting for invalid range, fixes #947 2019-05-27 12:25:18 +02:00
Miodrag Milanovic
34417ce55f Added support for unsized constants, fixes #1022 
Includes work from @sumit0190 and @AaronKel
 2019-05-27 11:42:10 +02:00
Eddie Hung
68359bcd6f Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux 2019-05-23 13:37:53 -07:00
Stefan Biereigel
85de9d26c1 fix assignment of non-wires 2019-05-23 17:55:56 +02:00
Stefan Biereigel
fd003e0e97 fix indentation across files 2019-05-23 13:57:27 +02:00
Stefan Biereigel
075a48d3fa implementation for assignments working 2019-05-23 13:57:27 +02:00
Stefan Biereigel
9df04d7e75 make lexer/parser aware of wand/wor net types 2019-05-23 13:57:27 +02:00
Eddie Hung
7057753427 Rename label 2019-05-21 18:20:31 -07:00
Eddie Hung
b5a29460b9 Try again 2019-05-21 17:20:19 -07:00
Eddie Hung
1bff09f2ff Fix warning 2019-05-21 16:26:20 -07:00
Eddie Hung
fb09c6219b Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
Kaj Tuomi
48ddbe52fb Read bigger Verilog files. 
Hit parser limit with 3M gate design. This commit fix it.
 2019-05-18 14:20:30 +03:00
Clifford Wolf
b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes 
Support for attributes on parameters and localparams for Verilog frontend
 2019-05-16 14:21:18 +02:00
Maciej Kurc
ce4a0954bc Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:44:16 +02:00