mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 01:55:33 +00:00
Code Activity

Merge pull request #1060 from antmicro/parsing_attr_on_port_conn

Browse source 
Added support for parsing attributes on port connections.
This commit is contained in:
Clifford Wolf 2019-06-06 12:34:05 +02:00 • committed by GitHub
commit b894187cf6
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
14 changed files with 279 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

24
frontends/verilog/verilog_parser.y
View file

@ -1532,27 +1532,31 @@ cell_port_list_rules:
cell_port | cell_port_list_rules ',' cell_port;
cell_port:
/* empty */ {
attr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
free_attr($1);
} |
expr {
attr expr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
node->children.push_back($1);
node->children.push_back($2);
free_attr($1);
} |
'.' TOK_ID '(' expr ')' {
attr '.' TOK_ID '(' expr ')' {
AstNode *node = new AstNode(AST_ARGUMENT);
node->str = *$2;
node->str = *$3;
astbuf2->children.push_back(node);
node->children.push_back($4);
delete $2;
node->children.push_back($5);
delete $3;
free_attr($1);
} |
'.' TOK_ID '(' ')' {
attr '.' TOK_ID '(' ')' {
AstNode *node = new AstNode(AST_ARGUMENT);
node->str = *$2;
node->str = *$3;
astbuf2->children.push_back(node);
delete $2;
delete $3;
free_attr($1);
};
always_stmt: