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yosys/frontends
Clifford Wolf b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes
Support for attributes on parameters and localparams for Verilog frontend
2019-05-16 14:21:18 +02:00
..
aiger Add log_debug() framework 2019-04-22 17:25:52 +02:00
ast Merge pull request #946 from YosysHQ/clifford/specify 2019-05-06 20:57:15 +02:00
blif Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
ilang Make the generated *.tab.hh include all the headers needed to define the union. 2019-05-14 21:07:26 -07:00
json Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
liberty Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
verific For hier_tree::Elaborate() also include SV root modules (bind) 2019-05-03 20:53:25 +02:00
verilog Merge pull request #1013 from antmicro/parameter_attributes 2019-05-16 14:21:18 +02:00