mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-26 09:24:37 +00:00
Code Activity
10620 commits 122 branches 59 tags 72 MiB
Commit graph

10620 commits

This branch
This branch
All branches
Author SHA1 Message Date
Claire Xen
527c681a2b
Merge pull request #2524 from bkbncn/patch-1 
Add boost-python3
 2021-03-01 17:46:33 +01:00
whitequark
7b47dd0f88
Merge pull request #2617 from RobertBaruch/doc 
RTLIL Documentation: switch in process is optional
 2021-03-01 08:10:32 -08:00
whitequark
ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict 
genrtlil: improve name conflict error messaging
 2021-03-01 08:10:19 -08:00
whitequark
0fb4224ebc
Merge pull request #2618 from zachjs/int-types 
sv: extended support for integer types
 2021-02-28 20:29:44 -08:00
Zachary Snow
0f5b646ab8 sv: extended support for integer types 
- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
 2021-02-28 16:31:56 -05:00
Robert Baruch
ca4b1afcb6 RTLIL Documentation: switch in process is optional 2021-02-27 09:58:03 -08:00
Claire Xen
d882b6fe3c
Update issue_template.md 2021-02-27 16:52:30 +01:00
Zachary Snow
bbff844acd genrtlil: improve name conflict error messaging 2021-02-26 18:08:23 -05:00
Michael Singer
d56b76bd7c Add tests for $countbits 2021-02-26 12:28:58 -05:00
Michael Singer
04b41ed04a Implement $countones, $isunknown and $onehot{,0} 2021-02-26 12:28:58 -05:00
Michael Singer
8434ba5a3b Implement $countbits function 2021-02-26 12:28:58 -05:00
Zachary Snow
22bed38540 Extend simplify() recursion warning 2021-02-26 12:11:23 -05:00
Marcelina Kościelnicka
5d0cc54f5c Bump version 2021-02-26 00:24:33 +01:00
whitequark
58a5755187
Merge pull request #2554 from hzeller/master 
Fix digit-formatting calculation for small numbers.
 2021-02-25 13:54:16 -08:00
Marcelina Kościelnicka
979347999f btor, smt2, smv: Add a hint on how to deal with funny FF types. 2021-02-25 22:04:04 +01:00
Marcelina Kościelnicka
a651204efa Fix handling of unique/unique0/priority cases in the frontend. 
Basically:

- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)

Fixes #2596.
 2021-02-25 21:53:58 +01:00
TimRudy
dcd9f0af23
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) 2021-02-24 15:48:15 -05:00
whitequark
fffbf651df
Merge pull request #2607 from zachjs/logger-error-atexit 
Fix double-free on unmatched logger error pattern
 2021-02-24 19:12:56 +00:00
Zachary Snow
5e439b6e3f Fix double-free on unmatched logger error pattern 
When an expected logger error pattern is unmatched, the logger raises
another (hidden) error. Because of the previous ordering of actions,
`logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()`
twice, causing a double-free.
 2021-02-23 20:49:21 -05:00
Marcelina Kościelnicka
b05b98521c Add tests for some common techmap files. 2021-02-24 01:07:34 +01:00
Marcelina Kościelnicka
cde73428b0 Fix syntax error in adff2dff.v 
Fixes #2600.
 2021-02-24 01:07:34 +01:00
Marcelina Kościelnicka
f4f471f342 frontend: Make helper functions for printing locations. 2021-02-23 23:51:52 +01:00
whitequark
ad2960adb7
Merge pull request #2594 from zachjs/func-arg-width 
verilog: fix sizing of constant args for tasks/functions
 2021-02-23 21:46:16 +00:00
Robert Baruch
4b31223e60 int -> bool 2021-02-23 17:52:43 +01:00
Robert Baruch
7c50b89b24 Adds is_wire to SigBit and SigChunk 
Useful for PYOSYS because Python can't easily check wire against NULL.
 2021-02-23 17:52:43 +01:00
William D. Jones
ae07298a6b machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
William D. Jones
353ace5034 machxo2: Update tribuf test to reflect active-low OE. 2021-02-23 17:39:58 +01:00
William D. Jones
8f1a350f5e machxo2: Add experimental status to help. 2021-02-23 17:39:58 +01:00
William D. Jones
e3974809ec machxo2: Add DCCA and DCMA blackbox primitives. 2021-02-23 17:39:58 +01:00
William D. Jones
a1ea1430b6 machxo2: Fix reversed interpretation of REG_SD config bits. 2021-02-23 17:39:58 +01:00
William D. Jones
4e9def23de machxo2: Tristate is active-low. 2021-02-23 17:39:58 +01:00
William D. Jones
8b14152506 machxo2: Fix typos in FACADE_FF sim model. 2021-02-23 17:39:58 +01:00
William D. Jones
8348c45e4f machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. 2021-02-23 17:39:58 +01:00
William D. Jones
120404bfda machxo2: Improve help_mode output in synth_machxo2. 2021-02-23 17:39:58 +01:00
William D. Jones
3674eb34d4 machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells. 2021-02-23 17:39:58 +01:00
William D. Jones
124780ecd9 machxo2: Add missing OSCH oscillator primitive. 2021-02-23 17:39:58 +01:00
William D. Jones
c31b17a2e2 machxo2: Add believed-to-be-correct tribuf test. 2021-02-23 17:39:58 +01:00
William D. Jones
c7aaa88f58 machxo2: Add passing fsm, mux, and shifter tests. 2021-02-23 17:39:58 +01:00
William D. Jones
453904dd00 machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. 2021-02-23 17:39:58 +01:00
William D. Jones
597a54dbd0 machxo2: Add -noiopad option to synth_machxo2. 2021-02-23 17:39:58 +01:00
William D. Jones
3697f351d5 machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. 2021-02-23 17:39:58 +01:00
William D. Jones
f07b8eb606 machxo2: Fix cells_sim typo where OFX1 was multiply-driven. 2021-02-23 17:39:58 +01:00
William D. Jones
c76f361b56 machxo2: synth_machxo2 now maps ports to FACADE_IO. 2021-02-23 17:39:58 +01:00
William D. Jones
03cbf1327d machxo2: Add initial value for Q in FACADE_FF. 2021-02-23 17:39:58 +01:00
William D. Jones
0364ded385 machxo2: Add FACADE_IO simulation model. More comments on models. 2021-02-23 17:39:58 +01:00
William D. Jones
1b703d3f03 machxo2: Add FACADE_SLICE simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones
cc52eb53cd machxo2: Improve FACADE_FF simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones
427fed23ee machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. 2021-02-23 17:39:58 +01:00
William D. Jones
19b043344c machxo2: Add dffe test. 2021-02-23 17:39:58 +01:00
William D. Jones
84937e9689 machxo2: Add dff.ys test, fix another cells_map.v typo. 2021-02-23 17:39:58 +01:00