4363 commits

Author	SHA1	Message	Date
Akash Levy	26d9bdb17c	Add more stuff to muxpack	2024-08-21 16:57:28 -07:00
Emily Schmidt	850b3a6c29	convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h	2024-08-21 11:04:08 +01:00
Emily Schmidt	8c0f625c3a	functional backend: topological sort starts with the output and next states nodes, other nodes get deleted	2024-08-21 11:03:29 +01:00
Emily Schmidt	bdb59ffc8e	add -fst-noinit flag to sim for not initializing the state from the fst file	2024-08-21 11:03:29 +01:00
Emily Schmidt	dd5ec84a26	fix bugs in drivertools	2024-08-21 11:01:09 +01:00
Jannis Harder	d4e3daa9d0	ComputeGraph datatype for the upcoming functional backend	2024-08-21 11:01:09 +01:00
Jannis Harder	68c3a47945	WIP temporary drivertools example	2024-08-21 11:01:08 +01:00
Akash Levy	58b3881845	Undo silly Yosys removal	2024-08-20 01:25:21 -07:00
Akash Levy	6cb3c3217c	Update Yosys to remove unnecessary passes	2024-08-19 21:45:29 -07:00
Akash Levy	56cfcdb9f6	Merge branch 'YosysHQ:main' into master	2024-08-19 17:12:02 -07:00
Emil J	e0d3bbf3c3	Merge pull request #4452 from phsauter/shiftadd-underflow-fix ... peepopt: avoid shift-amount underflow	2024-08-19 15:45:46 +02:00
Krystine Sherwin	7b47f645d7	Address warnings ... - Setting default values - Fixing mismatched types - Guarding unused var	2024-08-16 04:30:31 +12:00
Akash Levy	7345258738	Add shift left to operators that can be size-reduced based on size of output ports	2024-08-14 22:05:47 -07:00
Akash Levy	35c19cb391	Option to include unused bits attribute or not	2024-08-14 22:05:12 -07:00
Akash Levy	34e5bc1129	Merge branch 'YosysHQ:main' into master	2024-08-14 16:56:53 -07:00
Akash Levy	71a7f3fabd	Fix for segfaulting	2024-08-14 16:00:03 -07:00
Akash Levy	8118380726	Update to fix infinite loop	2024-08-14 13:40:30 -07:00
Akash Levy	83dfdd9dd5	Fix splitfanout	2024-08-14 13:19:58 -07:00
Akash Levy	63a421aed8	Small comment update	2024-08-14 05:37:28 -07:00
Akash Levy	2deabdd640	Make splitfanout more robust	2024-08-14 05:29:03 -07:00
Akash Levy	55782682de	Iterative muxpack	2024-08-14 05:27:50 -07:00
Akash Levy	5777bed8ed	Add splitfanout first pass	2024-08-14 03:24:24 -07:00
Martin Povišer	3057c13a66	Improve libparse encapsulation	2024-08-13 18:47:36 +02:00
Martin Povišer	78382eaa6f	libparse: Adjust whitespace	2024-08-13 18:47:36 +02:00
Akash Levy	953f405a84	Merge branch 'YosysHQ:main' into master	2024-08-07 11:47:52 -07:00
Martin Povišer	4c3203866f	exec: Add missing newline	2024-08-07 13:02:00 +02:00
George Rennie	236c69bed4	clk2fflogic: run peepopt -formalclk before processing design ... * this attempts to rewrite clock gating patterns into a form that is less likely to introduce combinational loops with clk2fflogic * can be disabled with -nopeepopt which is useful for testing clk2fflogic	2024-08-07 10:14:04 +01:00
George Rennie	2cb3b6e9b8	peepopt: add formal only peepopt to rewrite latches to ffs in clock gates ... * this is gated behind the -formalclk flag, which also disables the other synthesis focused optimizations	2024-08-07 10:01:45 +01:00
Akash Levy	36fb6e08c1	Make muxpack faster	2024-08-06 02:26:57 -07:00
Akash Levy	b4ae5e8574	Merge branch 'YosysHQ:main' into master	2024-08-05 11:02:17 -07:00
Miodrag Milanovic	6d98418f3d	Set ranges on exported wires in VCD and FST	2024-08-02 15:23:00 +02:00
Akash Levy	bafce0ddee	Revert SCC	2024-07-30 23:08:06 -07:00
Akash Levy	c0af4604bc	Update Yosys	2024-07-30 16:55:18 -07:00
Emil J	92cac63845	Merge pull request #4344 from widlarizer/emil/keep_hierarchy ... cost: add keep_hierarchy pass with min_cost argument	2024-07-29 16:33:08 +02:00
N. Engelhardt	9f869b265c	Merge pull request #4474 from tony-min-1/mchp ... Add PolarFire FPGA support	2024-07-29 15:28:44 +02:00
Emil J. Tywoniak	4b29f64142	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
Akash Levy	89630d3755	Merge branch 'YosysHQ:main' into master	2024-07-28 22:42:33 -07:00
N. Engelhardt	dd3637f9f0	Merge pull request #4506 from povik/synthprop-formatting ... synthprop: Reformat the help	2024-07-26 12:28:09 +02:00
Martin Povišer	7ee685a0b0	proc_rom: Set src on the emitted memory	2024-07-25 23:14:27 +01:00
Akash Levy	0a997b9e64	muxpack verbosity and -ignore_excl option	2024-07-25 04:40:37 -07:00
Martin Povišer	e063b96104	synthprop: Reformat the help	2024-07-25 11:43:58 +02:00
Martin Povišer	0cefe8a1e8	check: Skip detailed edge modeling if costly	2024-07-18 13:08:19 +02:00
Martin Povišer	e70b1251ad	check: Adjust prints	2024-07-18 13:08:19 +02:00
Martin Povišer	3f71bc469d	check: Rephrase comment	2024-07-18 13:08:19 +02:00
Akash Levy	a42f4dbedb	Merge branch 'YosysHQ:main' into master	2024-07-18 00:10:20 -07:00
Emil J	1166238c0f	Merge pull request #4176 from povik/opt_expr-performance ... Improve `opt_expr` performance	2024-07-15 16:10:25 +02:00
Emil J. Tywoniak	532188f239	opt_expr: change info message	2024-07-15 11:14:47 +02:00
Tony Min	d41688f7d7	Revisions (#4) ... * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>	2024-07-08 10:57:16 -04:00
Akash Levy	aec3df36d1	Make flatten less expressive	2024-07-07 21:46:23 -07:00
Akash Levy	c85b8a8a4d	Merge branch 'YosysHQ:main' into master	2024-07-06 15:12:11 -07:00