George Rennie 236c69bed4 clk2fflogic: run peepopt -formalclk before processing design ... * this attempts to rewrite clock gating patterns into a form that is less likely to introduce combinational loops with clk2fflogic * can be disabled with -nopeepopt which is useful for testing clk2fflogic		2024-08-07 10:14:04 +01:00
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cmds	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
equiv	equiv_simple: Take FFs into account for driver map	2024-02-21 12:05:52 +01:00
fsm	add option to fsm_detect to ignore self-resetting	2023-01-30 16:12:53 +01:00
hierarchy	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
memory	memory_map: Explain -iattr better	2024-03-06 15:15:37 +01:00
opt	Merge pull request #4176 from povik/opt_expr-performance	2024-07-15 16:10:25 +02:00
pmgen	peepopt: add formal only peepopt to rewrite latches to ffs in clock gates	2024-08-07 10:01:45 +01:00
proc	proc_rom: Set src on the emitted memory	2024-07-25 23:14:27 +01:00
sat	clk2fflogic: run peepopt -formalclk before processing design	2024-08-07 10:14:04 +01:00
techmap	cellmatch: add comments	2024-05-03 16:42:41 +02:00
tests	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00