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Revisions (#4)

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* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
This commit is contained in:
Tony Min 2024-07-08 10:57:16 -04:00 • committed by GitHub
parent 6fe0e00050
commit d41688f7d7
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44 changed files with 435 additions and 1118 deletions
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6
passes/pmgen/microchip_dsp.pmg
View file

@ -126,7 +126,7 @@ code sigA sigB sigD preAdderStatic moveBtoA
// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
// we basically swap it.
sigA = port(dsp, \B);
sigA = sigB;
}
// port B of preAdderStatic must be mapped to port D of DSP for subtraction
@ -368,7 +368,7 @@ match ff
filter !ff->type.in($adff, $adffe) || allowAsync
// clock must be consistent
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ
@ -415,7 +415,7 @@ match ff
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ

2
passes/pmgen/microchip_dsp_CREG.pmg
View file

@ -145,7 +145,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ