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https://github.com/YosysHQ/yosys
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Add splitfanout first pass
This commit is contained in:
Akash Levy
parent
fd53f4ab1b
commit
5777bed8ed
2 changed files with 195 additions and 0 deletions
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@ -15,6 +15,7 @@ OBJS += passes/cmds/scatter.o
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OBJS += passes/cmds/setundef.o
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OBJS += passes/cmds/splitnets.o
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OBJS += passes/cmds/splitcells.o
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OBJS += passes/cmds/splitfanout.o
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OBJS += passes/cmds/stat.o
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OBJS += passes/cmds/setattr.o
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OBJS += passes/cmds/copy.o
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194
passes/cmds/splitfanout.cc
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194
passes/cmds/splitfanout.cc
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@ -0,0 +1,194 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SplitfanoutWorker
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{
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Module *module;
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SigMap sigmap;
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dict<SigBit, tuple<IdString,IdString,int>> bit_drivers_db;
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dict<SigBit, pool<tuple<IdString,IdString,int>>> bit_users_db;
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SplitfanoutWorker(Module *module) : module(module), sigmap(module)
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{
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->output(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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bit_drivers_db[bit] = tuple<IdString,IdString,int>(cell->name, conn.first, i);
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}
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}
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}
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->input(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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if (!bit_drivers_db.count(bit)) continue;
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(cell->name,
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conn.first, i-std::get<2>(bit_drivers_db[bit])));
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}
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}
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}
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for (auto wire : module->wires()) {
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if (!wire->port_output) continue;
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SigSpec sig(sigmap(wire));
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for (int i = 0; i < GetSize(sig); i++) {
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SigBit bit(sig[i]);
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if (!bit_drivers_db.count(bit)) continue;
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(wire->name,
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IdString(), i-std::get<2>(bit_drivers_db[bit])));
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}
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}
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}
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int split(Cell *cell)
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{
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// Get output signal/port
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SigSpec outsig;
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IdString outport;
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if (cell->hasPort(ID::Y)) {
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outsig = sigmap(cell->getPort(ID::Y));
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outport = ID::Y;
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}
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else if (cell->hasPort(ID::Q)) {
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outsig = sigmap(cell->getPort(ID::Q));
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outport = ID::Q;
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}
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else
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return 0;
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// Check if output signal is "bit-split", skip if so
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pool<tuple<IdString,IdString,int>> bit_users = bit_users_db[outsig[0]];
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for (int i = 0; i < GetSize(outsig); i++) {
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if (bit_users_db[outsig[i]] != bit_users) {
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log(" Skipping %s cell %s/%s with bit-split output.\n", log_id(cell->type), log_id(module), log_id(cell));
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return 0;
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}
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}
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// Skip if output signal has only one user
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if (GetSize(bit_users) <= 1)
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return 0;
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// Iterate over bit users and create a new cell for each one
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log("Splitting %s cell %s/%s into %d copies based on fanout:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
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int foi = 0;
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cell->setPort(outport, module->addWire(NEW_ID, GetSize(outsig)));
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for (auto user : bit_users)
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{
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// Create a new cell
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IdString new_name = module->uniquify(cell->name.str());
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Cell *new_cell = module->addCell(new_name, cell);
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// Connect the new cell to the user
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if (std::get<1>(user) == IdString()) {
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Wire *old_wire = module->wire(std::get<0>(user));
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Wire *new_wire = module->addWire(NEW_ID, old_wire);
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module->swap_names(old_wire, new_wire);
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old_wire->port_id = 0;
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old_wire->port_input = false;
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old_wire->port_output = false;
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new_cell->setPort(outport, new_wire);
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}
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else {
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Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig));
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module->cell(std::get<0>(user))->setPort(std::get<1>(user), new_wire);
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new_cell->setPort(outport, new_wire);
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}
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// Log the new cell
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log(" slice %d: %s => %s\n", foi, log_id(new_name), log_signal(new_cell->getPort(outport)));
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// Increment the fanout index
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foi++;
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}
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// Remove the original cell
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module->remove(cell);
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// Fix up ports
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module->fixup_ports();
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// Return the number of new cells created
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return GetSize(bit_users)-1;
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}
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};
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struct SplitfanoutPass : public Pass {
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SplitfanoutPass() : Pass("splitfanout", "split up cells with >1 fanout into copies") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splitfanout [options] [selection]\n");
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log("\n");
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log("This command copies selected cells with >1 fanout into cells with fanout 1. It\n");
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log("is effectively the opposite of the opt_merge pass.\n");
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log("\n");
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log("This command operates only on cells with 1 output and no \"bit split\" on that\n");
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log("output.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing SPLITFANOUT pass (splitting up cells with >1 fanout into copies).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// No arguments currently supported
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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int count_split_pre = 0;
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int count_split_post = 0;
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while (1) {
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SplitfanoutWorker worker(module);
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bool did_something = false;
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for (auto cell : module->selected_cells()) {
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int n = worker.split(cell);
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did_something |= (n != 0);
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count_split_pre += (n != 0);
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count_split_post += n;
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}
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if (!did_something)
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break;
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}
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if (count_split_pre)
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log("Split %d cells in module '%s' into %d copies based on fanout.\n",
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count_split_pre, log_id(module), count_split_post);
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}
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}
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} SplitfanoutPass;
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PRIVATE_NAMESPACE_END
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