1667 commits

Author	SHA1	Message	Date
Eddie Hung	a7632ab332	Try using an ICE40_CARRY_LUT primitive to avoid ABC issues	2019-04-17 11:10:04 -07:00
Eddie Hung	17fb6c3522	Fix spacing	2019-04-17 08:40:50 -07:00
Eddie Hung	743c164eee	Add SB_LUT4 to box library	2019-04-16 17:34:11 -07:00
Eddie Hung	7980118d74	Add ice40 box files	2019-04-16 16:39:30 -07:00
Eddie Hung	cbb85e40e8	Add MUXCY and XORCY to cells_box.v	2019-04-16 14:53:28 -07:00
Eddie Hung	aece97024d	Fix spacing	2019-04-16 13:16:20 -07:00
Eddie Hung	53b19ab1f5	Make cells.box whiteboxes not blackboxes	2019-04-16 12:43:14 -07:00
Eddie Hung	5189695362	read_verilog cells_box.v before techmap	2019-04-16 12:41:56 -07:00
Eddie Hung	d259e6dc14	synth_xilinx: before abc read +/xilinx/cells_box.v	2019-04-16 11:21:46 -07:00
Eddie Hung	3ac4977b70	Add +/xilinx/cells_box.v containing models for ABC boxes	2019-04-16 11:21:03 -07:00
Eddie Hung	8c6cf07acf	Revert "Add abc_box_id attribute to MUXF7/F8 cells" ... This reverts commit 8fbbd9b129.	2019-04-16 11:14:59 -07:00
Eddie Hung	8fbbd9b129	Add abc_box_id attribute to MUXF7/F8 cells	2019-04-15 22:25:09 -07:00
Eddie Hung	538592067e	Merge branch 'xaig' into xc7mux	2019-04-15 22:04:20 -07:00
Diego	f9272fc56d	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	2019-04-12 23:40:02 -05:00
Eddie Hung	04e466d5e4	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	2019-04-12 12:28:37 -07:00
Eddie Hung	f77da46a87	Merge remote-tracking branch 'origin/master' into xaig	2019-04-12 12:21:48 -07:00
Eddie Hung	db1a5ec6a2	Merge pull request #928 from litghost/add_xc7_sim_models ... Add additional cells sim models for core 7-series primitives.	2019-04-12 11:52:45 -07:00
Eddie Hung	8228b593ef	Merge remote-tracking branch 'origin/master' into xc7mux	2019-04-12 09:46:07 -07:00
Keith Rothman	1f9235ede5	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-04-12 09:35:15 -07:00
Diego	643ae9bfc5	Fixing issues in CycloneV cell sim	2019-04-11 19:59:03 -05:00
Eddie Hung	233edf00fe	Fix cells_map.v some more	2019-04-11 10:48:14 -07:00
Eddie Hung	8658b56a08	More fine tuning	2019-04-11 10:08:05 -07:00
Eddie Hung	0ec8564099	Fix cells_map.v	2019-04-11 10:04:58 -07:00
Eddie Hung	bca3779657	Fix typo	2019-04-11 09:25:19 -07:00
Eddie Hung	87b8d29a90	Juggle opt calls in synth_xilinx	2019-04-11 09:13:39 -07:00
Eddie Hung	cd7b2de27f	WIP for cells_map.v -- maybe working?	2019-04-10 18:05:09 -07:00
Eddie Hung	3d577586fd	Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1	2019-04-10 16:15:23 -07:00
Eddie Hung	3f5dab0d09	Fix for when B_SIGNED = 1	2019-04-10 14:51:10 -07:00
Eddie Hung	32561332b2	Update doc for synth_xilinx	2019-04-10 14:48:58 -07:00
Eddie Hung	17a02df05c	ff_map.v after abc	2019-04-10 12:36:06 -07:00
Eddie Hung	1ec949d5ed	Tidy up	2019-04-10 09:02:42 -07:00
Eddie Hung	526aef9c2a	Move map_cells to before map_luts	2019-04-10 08:50:31 -07:00
Eddie Hung	e0b46eb4cb	WIP for $shiftx to wide mux	2019-04-10 08:49:55 -07:00
Eddie Hung	4dac9818bd	Update LUT delays	2019-04-10 08:49:39 -07:00
Eddie Hung	9a6da9a79a	synth_* with -retime option now calls abc with -D 1 as well	2019-04-10 08:32:53 -07:00
Eddie Hung	3e368593eb	Add cells.lut to techlibs/xilinx/	2019-04-09 14:33:37 -07:00
Eddie Hung	fd88ab5c83	synth_xilinx to call abc with -lut +/xilinx/cells.lut	2019-04-09 14:32:39 -07:00
Eddie Hung	b9e19071b8	Add delays to cells.box	2019-04-09 14:32:10 -07:00
Keith Rothman	e107ccdde8	Fix LUT6_2 definition. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-04-09 11:43:19 -07:00
Eddie Hung	f2042fc7c4	synth_xilinx with abc9 to use -box	2019-04-09 11:01:46 -07:00
Eddie Hung	2ae26b986c	Add techlibs/xilinx/cells.box	2019-04-09 10:58:58 -07:00
Eddie Hung	3fc474aa73	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	2019-04-09 10:06:44 -07:00
Keith Rothman	5e0339855f	Add additional cells sim models for core 7-series primatives. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-04-09 09:01:53 -07:00
Eddie Hung	bca3cf6843	Merge branch 'master' into xaig	2019-04-08 16:31:59 -07:00
Eddie Hung	1d526b7f06	Call shregmap twice -- once for variable, another for fixed	2019-04-05 17:35:49 -07:00
Eddie Hung	a5f33b5409	Move dffinit til after abc	2019-04-05 16:20:43 -07:00
Eddie Hung	0364a5d811	Merge branch 'eddie/fix_retime' into xc7srl	2019-04-05 15:46:18 -07:00
Eddie Hung	9758701574	Move techamp t:$_DFF_?N? to before abc call	2019-04-05 15:39:05 -07:00
Eddie Hung	23a6533e98	Retry	2019-04-05 15:31:54 -07:00
Eddie Hung	8b6085254a	Resolve @daveshah1 comment, update synth_xilinx help	2019-04-05 15:15:13 -07:00