mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-22 16:27:38 +00:00
Code Activity
16688 commits 120 branches 64 tags 47 MiB
Commit graph

16688 commits

This branch
This branch
All branches
Author SHA1 Message Date
Krystine Sherwin
4ba732d1dd analogdevices: Adding RBRAM2 and -tech 2026-02-20 10:57:45 +00:00
Krystine Sherwin
4ff97770f5 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-02-20 10:57:45 +00:00
Krystine Sherwin
e7eae91abf analogdevices: Update lutram.ys test 2026-02-20 10:57:45 +00:00
Krystine Sherwin
49e463bfcc analogdevices: Native LUTRAM primitives 2026-02-20 10:57:45 +00:00
Lofty
5cdda40f14 analogdevices: LUTRAM config 2026-02-20 10:57:45 +00:00
Lofty
3780857f59 analogdevices: update timing model 2026-02-20 10:57:45 +00:00
Lofty
e6849b081f I thought I removed this... 2026-02-20 10:57:45 +00:00
Lofty
d45282042e analogdevices: user retargeting 2026-02-20 10:57:45 +00:00
Lofty
0ee490041e analogdevices: more housekeeping 2026-02-20 10:57:45 +00:00
Lofty
1690678911 analogdevices: remove some extra cells! 2026-02-20 10:57:45 +00:00
Lofty
bdf767e65e test suite 2026-02-20 10:57:45 +00:00
Lofty
9055d99215 synth_analogdevices: remove scopeinfo cells 2026-02-20 10:57:45 +00:00
Lofty
80f7d0ee6f Create synth_analogdevices 2026-02-20 10:57:45 +00:00
Krystine Sherwin
094481739f memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-02-20 10:57:00 +00:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks 
aigerparse: add some bounds checks
 2026-02-20 11:53:49 +01:00
Emil J
74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 
Fix segfault from shift with 0-width signed arg.
 2026-02-20 11:53:05 +01:00
Emil J
53509a9b2a
Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion 
modtools: fix database sanity
 2026-02-20 10:49:28 +01:00
Miodrag Milanović
679156d323
Merge pull request #5686 from YosysHQ/version_bump 
Automatic version bump
 2026-02-19 09:52:22 +01:00
Emil J. Tywoniak
abc7563a35 modtools: add ModIndex unit test 2026-02-18 22:15:44 +01:00
Emil J. Tywoniak
c75d80905a modtools: fix database sanity on wire name swap 2026-02-18 21:23:21 +01:00
Gus Smith
29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges 
kernel/celledges: cover more cell types
 2026-02-18 07:50:41 -08:00
Miodrag Milanovic
5bb31485b7 Display repo and branch when applicable 2026-02-18 13:34:36 +01:00
Emil J. Tywoniak
62f19cb3a9 modtools: fix port_del db erase 2026-02-18 12:20:36 +01:00
Emil J
33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check 
blifparse: add bounds check
 2026-02-18 12:18:05 +01:00
Miodrag Milanovic
63068f9b8f count relative to version tag, and ignore non existing 2026-02-16 16:44:33 +01:00
Miodrag Milanović
ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default 
Run unit tests on make test
 2026-02-13 15:02:50 +01:00
Miodrag Milanovic
0090aa96b6 Remove version bump action 2026-02-13 14:22:33 +01:00
Miodrag Milanovic
adf8b6b0d8 Add +post to version if from tarbal 2026-02-13 14:22:10 +01:00
Miodrag Milanovic
c7d88ded94 Make version bump automatic 2026-02-13 14:21:41 +01:00
Chris Hathhorn
1e852cef16 Fix segfault from shift with 0-width signed arg. 
Fixes #5684.
 2026-02-12 22:03:42 -06:00
github-actions[bot]
e2f0c4d9a0 Bump version 2026-02-13 00:35:27 +00:00
Miodrag Milanovic
bb7aa7d208 Cleanup of yml files 2026-02-12 14:56:45 +01:00
Miodrag Milanović
e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Miodrag Milanovic
e5b3e9fc1f This one should run only vanilla-tests 2026-02-12 14:08:49 +01:00
Miodrag Milanovic
c6e48f4bea These are tests from other Makefile 2026-02-12 14:06:08 +01:00
Miodrag Milanovic
cc79c6a761 Support building out of tree, but keep always in tests/unit 2026-02-12 12:17:07 +01:00
Maxim Kudinov
b055ea05fd gowin: dsp: Add mult inference tests 2026-02-12 14:12:32 +03:00
Maxim Kudinov
5b94a97fb3 gowin: synth_gowin: Add -nodsp option 2026-02-12 13:58:47 +03:00
Maxim Kudinov
542b29fa6a gowin: synth_gowin: Merge flatten label with coarse 2026-02-12 13:58:47 +03:00
Maxim Kudinov
5ea073d45e gowin: format MULT instances 2026-02-12 13:35:49 +03:00
Miodrag Milanović
9b9e7b5ae3
Merge pull request #3389 from uwsampl/support-parameter-default-values-in-json-frontend-and-verilog-backend 
Support parameter default values in JSON frontend and Verilog backend
 2026-02-12 10:17:56 +01:00
Miodrag Milanović
ce5321da8c
Merge pull request #5682 from YosysHQ/update_abc 
Update ABC as per 2026-02-11
 2026-02-12 08:05:23 +01:00
github-actions[bot]
1319112913 Bump version 2026-02-12 00:32:36 +00:00
Gus Smith
7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Emil J
b890b1b43f
Merge pull request #5678 from YosysHQ/emil/remove-dockerfile 
Dockerfile: remove
 2026-02-11 17:32:21 +01:00
Miodrag Milanovic
a13b5c4211 Update ABC as per 2026-02-11 2026-02-11 17:30:08 +01:00
Gus Smith
be9c857e72 Fix ABC after merge 2026-02-11 08:12:38 -08:00
Gus Smith
b0021e5b10 Add tests 2026-02-11 08:10:57 -08:00
Gus Smith
1ede98797f Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith
9ad7aed4a5 Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00