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Code Activity
12625 commits 122 branches 59 tags 73 MiB
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3932 commits

Author SHA1 Message Date
whitequark
9eb03d458d opt_lut: show original truth table for both cells. 2018-12-07 17:04:41 +00:00
whitequark
a8ab722824 opt_lut: add -limit option, for debugging misoptimizations. 2018-12-07 16:36:26 +00:00
David Shah
1dfb2fecab abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 15:05:07 +00:00
Clifford Wolf
643f858acf Bugfix in opt_expr handling of a<0 and a>=0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:21 +01:00
whitequark
a9baee4b24 rename: add -src, for inferring names from source locations. 2018-12-05 20:35:13 +00:00
whitequark
d1f2cb01dc lut2mux: handle 1-bit INIT constant in $lut cells. 
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
 2018-12-05 19:27:48 +00:00
whitequark
88217d0157 opt_lut: simplify type conversion. NFC. 2018-12-05 19:12:02 +00:00
Clifford Wolf
2d98db73e3 Rename opt_lut.cpp to opt_lut.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-05 18:03:58 +01:00
whitequark
45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark
e603484070 opt_lut: always prefer to eliminate 1-LUTs. 
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
 2018-12-05 16:30:37 +00:00
whitequark
59eea0183f opt_lut: collect and display statistics. 2018-12-05 16:30:37 +00:00
whitequark
e54c7e951c opt_lut: refactor to use a worker. NFC. 2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
Clifford Wolf
c800e3bb16 Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-04 23:30:23 +01:00
Clifford Wolf
70c417174d
Merge pull request #702 from smunaut/min_ce_use 
Add option to only use DFFE is the resulting E signal would be use > N times
 2018-12-04 14:29:21 -08:00
Clifford Wolf
47c89d600c
Merge pull request #676 from rafaeltp/master 
Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
 2018-12-01 04:11:19 +01:00
Sylvain Munaut
8d3ab626ea dff2dffe: Add option for unmap to only remove DFFE with low CE signal use 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-27 21:50:42 +01:00
Clifford Wolf
ab97eddee9 Add iteration limit to "opt_muxtree" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 17:56:47 +01:00
Niels Moseley
cfc9b9147c DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info. 2018-11-06 12:11:52 +01:00
Clifford Wolf
719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Niels Moseley
04cd179696 Liberty file newline handling is more relaxed. More descriptive error message 2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a Report an error when a liberty file contains pin references that reference non-existing pins 2018-11-03 18:07:51 +01:00
rafaeltp
f8b97e21f3 using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal 2018-10-21 11:32:44 -07:00
rafaeltp
7b964bfb83 cleaning up for PR 2018-10-20 18:02:59 -07:00
rafaeltp
ce069830c5 fixing code style 2018-10-20 17:57:26 -07:00
rafaeltp
0ad4321781 solves #675 2018-10-20 17:50:21 -07:00
Ruben Undheim
436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Clifford Wolf
6514443a5c
Merge pull request #672 from daveshah1/fix_bram 
memory_bram: Reset make_outreg when growing read ports
 2018-10-19 16:09:11 +02:00
David Shah
3420ae5ca5 memory_bram: Reset make_outreg when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 14:46:31 +01:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
Ruben Undheim
c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
tklam
f4343b3dc7 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:24:24 +08:00
tklam
302edf0429 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:11:19 +08:00
Ruben Undheim
458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
tklam
b86eb3deef fix bug: pass by reference 2018-09-26 17:57:39 +08:00
TK Lam
2b89074240 Fix issue #639 2018-09-26 16:11:45 +08:00
Clifford Wolf
592a82c0ad
Merge pull request #625 from aman-goel/master 
Minor revision to -expose in setundef pass
 2018-09-14 12:36:13 +02:00
acw1251
5fe16c25b8 Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
Aman Goel
75c1f8d241 Minor revision to -expose in setundef pass 
Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
 2018-09-10 21:44:36 -04:00
Benedikt Tutzer
95d65971f3 added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile 2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d87c7df27f Two passes are not allowed to have the same filename 2018-08-20 15:28:09 +02:00
Benedikt Tutzer
6d18837d62 Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path 2018-08-20 15:11:06 +02:00
Clifford Wolf
05466790a6
Merge pull request #606 from cr1901/show-win 
`show` pass `-format` and `-viewer` improvements on Windows
 2018-08-19 15:25:46 +02:00
Aman Goel
83b41260f6 Revision to expose option in setundef pass 
Corrects indentation

Simplifications and corrections
 2018-08-18 09:08:07 +05:30
Aman Goel
61f002c908
Merge pull request #3 from YosysHQ/master 
Updates from official repo
 2018-08-18 08:18:40 +05:30
Benedikt Tutzer
d79a2808cf Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script 2018-08-16 16:00:11 +02:00
William D. Jones
7ce7ea2eb4 Update show pass documentation with Windows caveats. 2018-08-15 17:18:19 -04:00
William D. Jones
9f91c62348 Fix run_command() when using -format and -viewer in show pass. 2018-08-15 17:18:19 -04:00