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yosys/passes
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Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
..
cmds Merge pull request #625 from aman-goel/master 2018-09-14 12:36:13 +02:00
equiv Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
fsm Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
hierarchy Documentation improvements etc. 2018-10-13 20:34:44 +02:00
memory Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
opt Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
proc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
sat Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
techmap Merge pull request #591 from hzeller/virtual-override 2018-08-15 14:05:38 +02:00
tests Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00