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6319 commits

Author SHA1 Message Date
Eddie Hung
42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung
09411dd996 ice40_dsp to accept $__MUL16X16 too 2019-07-18 15:38:28 -07:00
Eddie Hung
266c1ae122 synth_ice40 to decompose into 16x16 2019-07-18 15:38:09 -07:00
Eddie Hung
2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00
Eddie Hung
802470746c Check if RHS is empty first 2019-07-18 15:22:00 -07:00
Eddie Hung
e22a752242 Make consistent 2019-07-18 15:21:23 -07:00
Eddie Hung
90ac147eb2 Do not autoremove ffP aor muxP 2019-07-18 15:02:41 -07:00
Eddie Hung
08fe63c61e Improve pattern matcher to match subsets of $dffe? cells 2019-07-18 14:08:18 -07:00
Eddie Hung
79d63479ea Improve A/B reg packing 2019-07-18 13:30:35 -07:00
Eddie Hung
e075f0dda0 Do not autoremove A/B registers since they might have other consumers 2019-07-18 13:22:22 -07:00
Eddie Hung
0727b2c902 Fix xilinx_dsp index cast 2019-07-18 13:18:04 -07:00
Eddie Hung
8326af5418 Fix signed multiplier decomposition 2019-07-18 13:11:26 -07:00
Eddie Hung
5562cb08a4 Use single DSP_SIGNEDONLY macro 2019-07-18 13:09:55 -07:00
Eddie Hung
2024357f32 Working for unsigned 2019-07-18 10:53:18 -07:00
Eddie Hung
d5cd2c80be Cleanup 2019-07-18 09:20:48 -07:00
Eddie Hung
c76607b9bc Wrong wildcard symbol 2019-07-18 08:14:58 -07:00
Eddie Hung
20b7120d66 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-18 08:11:33 -07:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels
synth_{ice40,ecp5}: more sensible pass label naming
2019-07-18 15:34:28 +02:00
Clifford Wolf
927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values
write_verilog: dump zero width constants correctly
2019-07-18 15:31:27 +02:00
David Shah
16b0ccf04c mul2dsp: Lower partial products always have unsigned inputs
Signed-off-by: David Shah <dave@ds0.me>
2019-07-18 11:33:37 +01:00
Eddie Hung
e3f8e59f18 Make all operands signed 2019-07-17 14:25:40 -07:00
Eddie Hung
58e63feae1 Update comment 2019-07-17 13:26:17 -07:00
Eddie Hung
91629ee4b3 Pattern matcher to check pool of bits, not exactly 2019-07-17 12:45:25 -07:00
Eddie Hung
8dca8d486e Fix mul2dsp signedness 2019-07-17 12:44:52 -07:00
Eddie Hung
1b62b82e05 A_SIGNED == B_SIGNED so flip both 2019-07-17 11:34:18 -07:00
Eddie Hung
d63f105708 SigSpec::remove_const() to return SigSpec& 2019-07-17 10:44:11 -07:00
Clifford Wolf
56c00e871f Remove old $pmux_safe code from write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-17 11:49:04 +02:00
David Shah
82153059a1
Merge pull request #1204 from smunaut/fix_1187
ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
2019-07-17 07:55:26 +01:00
Eddie Hung
0b6d47f8bf Add DSP_{A,B}_SIGNEDONLY macro 2019-07-16 15:55:13 -07:00
Eddie Hung
c501aa5ee8 Signedness 2019-07-16 15:54:27 -07:00
Eddie Hung
3f677fb0db Signed extension 2019-07-16 15:54:07 -07:00
Sylvain Munaut
f28e38de99 ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-07-16 23:57:15 +02:00
Eddie Hung
6390c535ba Revert drop down to 24x16 multipliers for all 2019-07-16 14:30:25 -07:00
Eddie Hung
569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
Eddie Hung
9616dbd125 Add support {A,B,P}REG packing 2019-07-16 14:06:32 -07:00
Eddie Hung
d086dfb5b0 SigSpec::extract to allow negative length 2019-07-16 14:06:07 -07:00
Eddie Hung
5d1ce04381 Add support for {A,B,P}REG in DSP48E1 2019-07-16 14:05:50 -07:00
whitequark
4ff44d85a5 write_verilog: dump zero width constants correctly.
Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).
2019-07-16 21:00:09 +00:00
Eddie Hung
f8e470c1d1
Merge pull request #1202 from YosysHQ/cmp2lut_lut6
cmp2lut transformation to support >32 bit LUT masks
2019-07-16 13:52:43 -07:00
whitequark
698ab9beee synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
whitequark
ba099bfe9b synth_{ice40,ecp5}: more sensible pass label naming. 2019-07-16 20:41:51 +00:00
Eddie Hung
7a58ee78dc gen_lut to return correctly sized LUT mask 2019-07-16 12:45:29 -07:00
Eddie Hung
8a2a2cd035 Forgot to commit 2019-07-16 12:44:26 -07:00
Eddie Hung
dd10d2b00d Add tests for cmp2lut on LUT6 2019-07-16 12:11:59 -07:00
David Shah
d38df68d26 xilinx: Add correct signed behaviour to DSP48E1 model
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 17:53:08 +01:00
Eddie Hung
5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
2019-07-16 08:53:47 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
David Shah
95c8d27b0b xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:47:53 +01:00
David Shah
8da4c1ad82 mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:44:40 +01:00
David Shah
7a75f5f3ac mul2dsp: Fix indentation
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:19:32 +01:00