Emil J. Tywoniak
3a5c492e32
clk2fflogic: fully cover $dffsr tests
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
1d468962b7
satgen, calc: $priority perform more x-bit horrors
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
6a5d74d252
satgen: $priority perform more x-bit horrors
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
39d960344b
satgen: $priority match x-prop against simplemap
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
ed58bb6bb4
clk2fflogic: $dffsr has undef output on S&R
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
3ea5437298
satgen: $priority can't have x on any output bit above an active input bit
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
dcd73b6b03
verilog_backend: alter only design copy unless -wreck
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
f785b664af
verilog_backend: simplemap $priority, ruining everything
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
f528e1cea1
simplemap: add $priority
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
a7286ca8f5
simlib: fix $priority
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
8192cee0b3
proc_dff: narrow $priority
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
d027b62d1c
proc_dff: fix missing polarity parameters for $dffsr, add another fallback
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
6e280c0e0b
proc_dff: uniquing $priority
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
e139970a38
proc_dff: fix enables for $dffsr
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
b77a93f816
proc_dff: emit $dffsr with $priority instead of mux tree
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
92d1a31162
proc_dff: refactor
2026-01-21 14:48:32 +01:00
Emil J. Tywoniak
7e664834b3
add POLARITY parameter to $priority cell
2026-01-21 14:06:33 +01:00
Emil J. Tywoniak
e166dd4475
add $priority cell
2026-01-21 13:46:32 +01:00
github-actions[bot]
967b47d984
Bump version
2026-01-15 00:24:54 +00:00
nella
763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string
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Add rtlil string getters
2026-01-14 19:00:47 +01:00
nella
210b733555
Add rtlil string getters
2026-01-14 15:37:18 +01:00
github-actions[bot]
4c1a18f01d
Bump version
2026-01-14 06:40:44 +00:00
Emil J
71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log
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read_verilog: remove log I left behind by accident
2026-01-13 17:48:30 +00:00
Emil J. Tywoniak
83c1364eeb
read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00
Emil J
8da113b7f0
Merge pull request #5502 from YosysHQ/emil/digit-separator
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Use digit separators for large decimal integers
2026-01-13 17:42:24 +00:00
Emil J
d9956b20f8
Merge pull request #5603 from YosysHQ/emil/makefile-no-ast-header
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Makefile: no longer install ast.h and ast_binding.h
2026-01-13 17:18:40 +00:00
Emil J
ff3c24fcdc
Merge pull request #5521 from YosysHQ/emil/merge-queues
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.github: trigger everything that triggers on main or PRs on merge queue
2026-01-13 17:22:37 +01:00
Emil J
5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire
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Add autowires in genblk/for expension
2026-01-13 16:40:22 +01:00
Emil J. Tywoniak
8e2038c419
Use digit separators for large decimal integers
2026-01-13 16:38:12 +01:00
Emil J. Tywoniak
21e6833010
Makefile: no longer install ast.h and ast_binding.h
2026-01-13 16:33:11 +01:00
Miodrag Milanović
8f00c1824f
Merge pull request #5602 from YosysHQ/year_update
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Update year in banner and license
2026-01-13 15:30:42 +01:00
Miodrag Milanovic
0e6973037d
Update year in banner and license
2026-01-13 14:23:51 +01:00
nella
b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg
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More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
2026-01-13 12:00:06 +01:00
Miodrag Milanović
77005b69a2
Merge pull request #5601 from YosysHQ/release/v0.61
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Release version 0.61
2026-01-13 09:39:50 +01:00
Miodrag Milanovic
b08e044994
Next dev cycle
2026-01-13 09:24:49 +01:00
Miodrag Milanovic
5ae48ee25f
Release version 0.61
2026-01-13 08:35:02 +01:00
Miodrag Milanović
51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux
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musllinux fix so wheels build can work
2026-01-13 07:08:04 +01:00
github-actions[bot]
78cbc21b94
Bump version
2026-01-13 00:22:49 +00:00
Emil J
cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux
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add lut2bmux
2026-01-12 16:09:13 +01:00
Miodrag Milanovic
b3b71df07c
musllinux fix so wheels build can work
2026-01-12 15:38:45 +01:00
Miodrag Milanović
72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix
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musllinux fix so wheels build can work
2026-01-12 14:00:00 +01:00
Emil J
f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround
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Check for missing port in SDC code to work around compiler bug
2026-01-12 11:22:25 +01:00
Miodrag Milanovic
2b12b74121
musllinux fix so wheels build can work
2026-01-11 15:23:38 +01:00
Robert O'Callahan
37347aacb2
Check for missing port in SDC code
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I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.
Anyway this code seems fine to have.
2026-01-10 04:00:17 +00:00
github-actions[bot]
991e704899
Bump version
2026-01-09 00:26:46 +00:00
KrystalDelusion
cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch
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Improve handling of empty switches
2026-01-09 11:52:27 +13:00
Emil J
c7b839ef5a
Merge pull request #5530 from rocallahan/parallel-opt-merge
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Parallelize `opt_merge`
2026-01-08 10:43:44 +01:00
Robert O'Callahan
8da919587d
Parallelize opt_merge.
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I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
2026-01-08 04:21:39 +00:00
github-actions[bot]
35321cd292
Bump version
2026-01-07 00:25:36 +00:00
Krystine Sherwin
9a09758f56
Test empty switches
2026-01-07 13:21:33 +13:00
