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simlib: fix $priority

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Emil J. Tywoniak 2026-01-19 18:57:52 +01:00
parent 8192cee0b3
commit a7286ca8f5
2 changed files with 19 additions and 2 deletions
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20
techlibs/common/simlib.v
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@ -3259,10 +3259,26 @@ endmodule
//- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
//-
module \$priority (A, Y);
parameter WIDTH = 8;
parameter WIDTH = 0;
parameter POLARITY = 0;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A & (~A + 1);
wire [WIDTH-1:0] tmp;
wire [WIDTH-1:0] A_active;
wire [WIDTH-1:0] Y_active;
assign A_active = A ^ ~POLARITY;
assign Y = Y_active ^ ~POLARITY;
genvar i;
generate
if (WIDTH > 0) begin
assign tmp[0] = A_active[0];
assign Y_active[0] = A_active[0];
end
for (i = 1; i < WIDTH; i = i + 1) begin
assign Y_active[i] = tmp[i-1] ? 1'b0 : A_active[i];
assign tmp[i] = tmp[i-1] | A_active[i];
end
endgenerate
endmodule

1
techlibs/common/techmap.v
View file

@ -694,6 +694,7 @@ module \$priority (A, Y);
wire [WIDTH-1:0] tmp;
(* force_downto *)
wire [WIDTH-1:0] A_active;
(* force_downto *)
wire [WIDTH-1:0] Y_active;
assign A_active = A ^ ~POLARITY;
assign Y = Y_active ^ ~POLARITY;