mirror of
https://github.com/YosysHQ/yosys
synced 2026-01-28 12:58:44 +00:00
verilog_backend: simplemap $priority, ruining everything
This commit is contained in:
parent
f528e1cea1
commit
f785b664af
1 changed files with 1 additions and 0 deletions
|
|
@ -2680,6 +2680,7 @@ struct VerilogBackend : public Backend {
|
|||
if (!noexpr) {
|
||||
Pass::call(design, "bmuxmap");
|
||||
Pass::call(design, "demuxmap");
|
||||
Pass::call(design, "simplemap t:$priority");
|
||||
}
|
||||
Pass::call(design, "clean_zerowidth");
|
||||
log_pop();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue