Emil J. Tywoniak
383daa1eb3
proc_mux: include switch expression location in $eq src
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
53585db9f7
kernel: add SwitchRule signal_src
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
85a17b0366
docs: workaround for warning from dump
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
a24c260998
proc_mux, genrtlil: make use of case_src for better case condition vs block tracking
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
a217a5c716
rtlil: add case_src to CaseRule
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
502ba3734b
proc_mux: copy switch src to _CMP wire
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
da65a18f39
proc_mux: copy mux src to Y port
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
ee800087e8
proc_mux: add comments
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
b3aea1b5d2
proc_mux: optimize source map locality for index density
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
4072bcfd0b
proc_dff: add wire src attributes to dff cells
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
f4a69805ae
verific: use SyncActions
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
469083dcaa
proc_mux: default to case src when action src is missing
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
a2e8e352b6
proc_mux: add src test
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
985e98935f
docs: word_mux grammar
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
778a667a91
proc_mux: refactor
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
cacd584347
proc_mux: emit fused action location src attributes on procmuxes
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
c36370f227
rtlil: add source tracking to CaseRule actions
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
5ec1cc0dec
gowin: lower LUT count sensitivity
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
7713b5a811
verilog: fix case location
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
94a53e08bc
rtlil: replace SigSig actions with new type SyncAction
2026-01-26 12:50:51 +01:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word
...
lut2mux: add -word option
2026-01-23 17:24:41 +01:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix
...
abc: handle ABC script errors instead of hanging
2026-01-23 07:16:48 +13:00
KrystalDelusion
98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages
...
Document nesting packages as unsupported
2026-01-23 07:16:22 +13:00
github-actions[bot]
a6fc695522
Bump version
2026-01-22 00:28:34 +00:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon
...
Add debugon pass for persistent debug logging
2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree
...
Add opt_balance_tree pass
2026-01-21 17:34:08 +01:00
Miodrag Milanović
2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy
...
Avoid spurious copy in `IdStringCollector::trace_named()`
2026-01-21 08:30:07 +01:00
Robert O'Callahan
2c0448a81b
Avoid spurious copy in IdStringCollector::trace_named()
2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f
Bump version
2026-01-21 00:27:51 +00:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017
...
verific: add explicit System Verilog 2017 option
2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6
verific: Fix -sv2017 message and formatting
2026-01-20 08:07:26 +01:00
github-actions[bot]
49e5950791
Bump version
2026-01-20 00:26:10 +00:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc
2026-01-20 05:56:14 +13:00
Miodrag Milanovic
cc3038f468
verific: Fix -sv2017 message
2026-01-19 16:32:46 +01:00
Miodrag Milanović
2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc
...
Update ABC as per 2026-01-19
2026-01-19 15:45:02 +01:00
nella
67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description
...
consteval: describe
2026-01-19 14:56:24 +01:00
Miodrag Milanovic
691983be14
Update ABC as per 2026-01-19
2026-01-19 12:08:24 +01:00
Emil J
7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs
...
docs: shuffle and expand contributing info
2026-01-19 12:02:49 +01:00
Emil J. Tywoniak
c3f36afe7f
opt_balance_tree: mark experimental
2026-01-19 12:01:25 +01:00
Emil J. Tywoniak
befadf6d4d
consteval: describe
2026-01-19 12:00:18 +01:00
Miodrag Milanović
9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning
...
Fix warning about unused variable in `dffunmap`.
2026-01-19 08:24:48 +01:00
Robert O'Callahan
28c199fbbd
Fix warning about unused variable in dffunmap.
2026-01-19 03:25:09 +00:00
KrystalDelusion
8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err
...
Improve error handling in sim
2026-01-19 09:51:12 +13:00
Miodrag Milanovic
d095d2c405
verific: add explicit System Verilog 2017 option
2026-01-16 07:56:53 +01:00
Natalia
ed64df737b
Add -on/-off modes to debug pass
2026-01-15 12:07:26 -08:00
Natalia
d5e1647d11
fix tests with truncation issues
2026-01-14 18:03:30 -08:00
github-actions[bot]
967b47d984
Bump version
2026-01-15 00:24:54 +00:00
Natalia
305b6c81d7
Refine width check to allow Y_WIDTH >= natural width
...
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).
This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
2026-01-14 14:58:53 -08:00
Natalia
60ac3670cb
Fix truncation issue in opt_balance_tree pass
...
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.
For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)
Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
2026-01-14 13:14:56 -08:00
nella
763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string
...
Add rtlil string getters
2026-01-14 19:00:47 +01:00
